DECchip 21050 Pass-Two Errata List ---------------------------------- 1. ADDRESS BOUNDARY DISCONNECT Issue: During a particular sequence of events the DECchip 21050 may miss an address disconnect boundary by one PCI data phase. The address disconnect boundary may be either a 256 Dword (1Kbyte) address boundary or a cache line address boundary. When the disconnect boundary is missed by the DECchip 21050 and additional specific circumstances occur, a single Dword of data can be delivered to the wrong address. These conditions are described below. 256 Dword Boundary: In order for the 21050 to miss the disconnect on the 256 dword address boundary, the following situation must exist: o a prefetchable read in the same direction must immediately precede the posted write o the end of the prefetchable read transaction on the target bus must overlap the start of the posted write on the initiating bus by one and only one cycle o the lowest 10 bits of the address of the posted write must be 3FC hex. o the posted write must request two or more dword transfers The intended behavior under these circumstances is that the 21050 would disconnect the posted write after the first data transfer (on the 256 dword boundary). What occurs in the above situation is that the 21050 disconnects the transaction after the second data transfer. Both dwords will be posted in the DECchip 21050. The 21050 will then initiate a write transaction to deliver the posted write data to the target. In addition to the above, if the following situation also occurs, the 21050 may deliver the second dword to the wrong address: o the target disconnects the above posted write initiated by the 21050 on the first dword, forcing the 21050 to initiate a second write transaction to deliver the second dword. Instead of correctly incrementing the address, the bottom 10 bits go to zero while the top 22 bits stay the same. As a result, the second dword will be written to the wrong address. Cache Line Size Boundary: In order for the 21050 to miss the disconnect on a cache line size address boundary, the following situation must exist: o the Cache Line Size register is set to a value between 1 and 15 o a prefetchable read in the same direction must immediately precede a posted memory write and invalidate command o the end of the prefetchable read transaction on the target bus must overlap the start of the posted memory write and invalidate on the initiating bus by one cycle o the address of the memory write and invalidate transaction must be 1 dword below a cache line size boundary o the posted memory write and invalidate must request two or more dword transfers The intended behavior under these circumstances is that the 21050 would disconnect the posted memory write and invalidate after the first data transfer (on the cache line boundary). What occurs in the above situation is that the 21050 disconnects the transaction after the second data transfer. Both posted dwords will be delivered to the target. Note: Masters using the Memory Write and Invalidate command should not attempt to cross a cache line boundary. So, under normal circumstances this disconnect scenario should not occur. All data will be delivered to the correct address, unless this cache line boundary coincides with a 256 dword boundary, where the contingencies in that section apply. Possible workarounds for the boundary disconnect problem: Software -------- 1. Modify the driver so that posted writes will never cross the 1KByte address boundary during a single transaction. If a posted write transaction has the low ten address bits equal to 3FC hex, then it should be a single burst transaction. Works for option cards implementations only. This appears to be the most desirable solution. 2. Set the cache line size equal to 2. Works if the memory read or memory read line command is used. Limits these reads to two data phase bursts. Limits memory write and invalidate transactions to two bursts, but does not affect memory write transactions. Do not use if memory read multiple command is used, unless the prefetch disable bit is also set (for upstream reads) or the address is mapped into non-prefetchable space (for downstream reads). This eliminates the possibility of the one cycle overlap which causes the disconnect problem. Caveat: assumes that single burst reads will not have master stalls on the first data cycle. 3. Set the burst limit counter equal to 2 (devices specific configuration register). This affects all read and write transactions, limiting the number of data cycles in a single transaction to 2. This eliminates the possibility of the one cycle overlap which causes the disconnect problem. If the Cache Line Size is set to a value greater than 2, all memory write and invalidate commands will be converted to memory write commands. Caveat: assumes that single burst reads will not have master stalls on the first data cycle. 4. Set the prefetch disable bit and map all downstream memory into non-prefetchable space. Works for memory read commands, limiting them to one burst. If memory read line or memory read multiple is used, then either the cache line size or the burst count must also be set to 2. Does not affect writes, unless the cache line size is also set to 2, which will limit memory write and invalidate transactions to 2 bursts. 5. Keep posting disabled (no posted writes, limited to a single transfer) by asserting the s_dispst_l pin and setting the Posting Disable bit. Does not affect reads. Hardware 6. Implement an external arbitration solution for the secondary bus (assuming DMA transfers are initiated on the secondary bus) that does the following: when a memory read type of transaction is detected, do not award any secondary bus grants until 15 clock cycles after the read transaction completes. This ensures that there will be no overlap under worst case latency conditions. 7. Implement the following external logic: when a memory read type of transaction is detected on the secondary bus, assert the s_dispst_l pin. Deassert the s_dispst_l pin the cycle after the next transaction starts (one cycle after next s_frame_l assertion). Make sure that the disable posting bit in 21050 configuration space (address 40, bit <1>) is set. This ensures that the next transaction, if it is a write, will be disconnected after one data phase completes. 2. VGA FRAME BUFFER MAPPING Issue: The DECchip 21050 supports forwarding of VGA frame buffer memory addresses from the primary to the secondary interface when the VGA Mode bit is set. VGA frame buffer memory ranges from 000A0000 hex to 000BFFFF hex. In the pass 2 implementation, memory reads to these locations are treated as prefetchable memory reads - read data can be prefetched for multi-transfer requests. In addition, the read byte enables will be forced to zero. If the read request is for a single data transfer (FRAME# is only asserted for one cycle), no prefetching will occur. However, the byte enables will still be forced to zero on the secondary bus. The pass 3 implementation will treat memory read accesses to frame buffer memory as non-prefetchable. When the memory read command is used, the 21050 will disconnect after a single data transfer and read byte enables will be forwarded to the secondary interface.