Dear Alpha DEC Groups:
I have few questions about the architecture of the DEC Alpha processor,
Would you please answer me or give me the exact site to search about.
I am saying exact site, because I have searched the site already and
couldn't find the answers.
1-How many address pins go out of the processor chip? How about data
pins? How many bits for an integer register? Is the processor RICS?
2- Does the processor uses logical or virtual cache, split cache or
unified cache?
3- What is the on chip cache size? what is the cache organization
(direct-mapping or set-associative) Does it use writeback or write
through policy?
4- Is the processor superscalar? If yes, how many issues at the same time?
5- Does the processor support dynamic instruction scheduling? and how?
Thank you
Nahid Amin
Received on Thu Nov 06 1997 - 19:22:02 NZDT