Hi,
This is just a revamped version of what appeared previously, taking into
account some later comments.
Where does the APW fit.
(a) J C King wrote that Dec are retiring most if not all the AS range.
(b) with the same amount of cache and same clock the APW was only
marginally slower than the AS.
I guess the APW is seen as the replacement for the AS.
Performance did not seem to be a problem.
Cache:
The cache size on the Alpha Personal Workstation can be either 0 or 2mb
(ie cache appears to be optional), where as the AlphaStation comes with
2mb standard unless its a 500/500 when 8mb is standard. So in most
situations the cache can be matched at 2mb on both platforms (it just
needs to be specifically ordered for the APW).
Someone suggested that if you have cache intensive code, (I guess with a
lot of data, or badly optimised code), the APW can be run with no cache
to remove any "out of cache" messages.
Marco Luchini wrote that there was twice the memory bandwidth on an AS
as a APW. Not sure what the size of the path is, I would have thought a
64 bit machine could only have a 64 bit memory path, perhaps a 128 path
if it could handle 2 intstructions at once as may be the case with a
super pipelined machine.
There was some indication that the cache on the APW was better matched
to the cpu, again I've got no idea on that.
CPU.
The cpu in the APW has the same number as the cpu in the AS. Not sure
that that guarantees the same basic functionality on both architectures,
I assume that it does. Obviously the chip can be clocked at the same
speeds on both the APW and the AS, so there is no advantage I assume
there.
Overall speed:
There was a suggestion that the AS500/500 (an 8mb cache machine) ran 45%
- 200% faster than an APW 500au, not sure about this. Ian Mortimer,
(mortimer_at_physics.uq.edu.au) has a model that runs 15% faster for small
models on an AS500/500 (8mb cache) over a APW 433Mhz au, 200% for medium
models and sometimes slower for large models. This might mean that as
the cache misses increase the wider memory bandwidth of the au means
that it can outperform the AS500/500.
DEC has published performance figures, try looking at
http://www.digital.com/hpc/news/news_spec_november18.html
The au numbers don't look that bad.
Scsi
It was pointed out by Tom Blinn (Unix Software Group DEC) that even
though the DEC Systems and Options catalogue stated that the "Maximum
number of Scsi controllers supported per system" for the au-series was 1
"Q-Logic 1040B Ultra Wide SCSI Controller" that there were no
restrictions in Digital Unix on adding a second Scsi Controller to an
APW. He left it a little unclear as to what DEC would do as far as
guarantees go, if someone where to just go ahead and do it.
One reply suggested that they had to run the scsi at fast scsi II for
their 2x23gb HDD's, meaning I guess that they were forced to go narrow
(ie 8bit) and so they didn't get upto Ultra speeds. I know that the scsi
bus is limited by the capabilities of the slowest device on the bus. A
further reply suggested that that particular user probably came up
against the scsi bus length limit for Ultra Scsi.
Future:
There was an indication that DEC was going to rationalise further, with
standardisation on shapes and boards across their Intel and Alpha
ranges. Part of this rationalisation may be the retirement of the AS
series.
Dennis
mcdonell_at_auslig.gov.au
Received on Mon Dec 22 1997 - 08:41:20 NZDT