Hello,
The server is the 2CPU AS2100 5/300 running du4.0d (patch set 1
installed) and the firmware is v5.1. Every once in a while it
is reporting uncorrectable "CPU Machine Check Errors" and the
CPU minor class is "660 Entry". Also, after the installation
of 4.0d and the patch set 1 the "110. Generalized Machine
State Type" appears during booting. It refers to a frame which
is not recognized.
I have tried hard to decipher the dia's output, but it seems I'm
missing something (or all of it). Is it memory or some other
subsystem? Is it the SWXCR which (as noted in the other message)
asks for a restart from time to time?
I'll attach 3 entries (sorry for wasting bandwidth) from dia.
It is interesting that the server didn't panic apart from one
last time when the panic string was "panic (cpu 0): System
Uncorrectable Machine Check 660". It has happened around 4:20AM,
at the time when the SWXCR is usually failing.
Thanks for your time.
Cheers.
Dejan Muhamedagic dejan_at_yunix.co.yu
******************************** ENTRY 3 ********************************
Logging OS 2. Digital UNIX
System Architecture 2. Alpha
Event sequence number 0.
Timestamp of occurrence 29-SEP-1998 04:26:35
Host name panda
System type register x00000009 AlphaServer 2x00
Number of CPUs (mpnum) x00000001
CPU logging event (mperr) x00000000
Event validity 1. O/S claims event is valid
Event severity 5. Low Priority
Entry type 110. Generalized Machine State Type
SWI Minor class 3. System configuration
========================
** SYSTEM CONFIG ********
Entry Length x0AE53967
Packet Rev x00000000
- - - - - - - - - - - -
Module ID Register x4B4A4B38 FRU Module Type --------- NOT Recognized
FRU Module -------------- FRR NOT
Recognized
Self Test --------------- NOT Valid code
** Frame NOT Recognized
SW Rev x0004
HW Rev P~
*** END Frame *** x00004C4B
******************************** ENTRY 4 ********************************
Logging OS 2. Digital UNIX
System Architecture 2. Alpha
Event sequence number 7.
Timestamp of occurrence 29-SEP-1998 04:22:42
Host name panda
System type register x00000009 AlphaServer 2x00
Number of CPUs (mpnum) x00000002
CPU logging event (mperr) x00000000
Event validity 1. O/S claims event is valid
Event severity 1. Severe Priority
Entry type 100. CPU Machine Check Errors
CPU Minor class 2. 660 Entry
-- ENTRY FRAME FOLLOWS --
Frame ID x00000022 Machine Check Frame
CPU Number Logging Event 0.
- ALPHA EV5 COMMON REGS -
Flags: x00000000
Machine Check Error Code x00000202 CPU Detected Unrecoverable Error
PAL SHADOW REG 0 x0000000000000000
PAL SHADOW REG 1 x0000000000000000
PAL SHADOW REG 2 x0000000000000000
PAL SHADOW REG 3 x0000000000000000
PAL SHADOW REG 4 x0000000000000000
PAL SHADOW REG 5 x0000000000000000
PAL SHADOW REG 6 x0000000000000000
PAL SHADOW REG 7 x0000000000000000
PALTEMP0 x0000000000000007
PALTEMP1 xFFFFFC00005FFF10
PALTEMP2 xFFFFFC0000482280
PALTEMP3 x0000000000004200
PALTEMP4 xFFFFFC0000602D70
PALTEMP5 xFFFFFC00005E04C8
PALTEMP6 xFFFFFC00006314D8
PALTEMP7 xFFFFFC0000481BA0
PALTEMP8 x1F1E161514020100
PALTEMP9 xFFFFFC0000481FC0
PALTEMP10 xFFFFFC000048A524
PALTEMP11 xFFFFFC0000481E20
PALTEMP12 xFFFFFC00004821F0
PALTEMP13 x0000012000000120
PALTEMP14 x0000000000000001
PALTEMP15 x0000000000000000
PALTEMP16 x0000020306600001
PALTEMP17 x0000000000000000
PALTEMP18 x0000000000000000
PALTEMP19 xFFFFFFFFA048F9D8
PALTEMP20 x000000000077A000
PALTEMP21 xFFFFFC0000482220
PALTEMP22 xFFFFFC0000603300
PALTEMP23 x000000001FC55A38
Exception Address Reg xFFFFFC000048A524
Native-mode Instruction
Exception PC x3FFFFF0000122949
Exception Summary Reg x0000000000000000
Exception Mask Reg x0000000000000000
PAL Base Address Reg x0000000000014000
Base Addr for PALcode: x0000000000000005
Interrupt Summary Reg x0000000000D00000
External HW Interrupt at IPL20
External HW Interrupt at IPL22
External HW Interrupt at IPL23
AST Requests 3-0: x0000000000000000
IBOX Ctrl and Status Reg x0000004160800000
Timeout Counter Bit Clear.
IBOX Timeout Counter Enabled.
Floating Point Instructions will Cause
FEN Exceptions.
PAL Shadow Registers Enabled.
Correctable Error Interrupts Enabled.
ICACHE BIST (Self Test) Was Successful.
Icache Par Err Stat Reg x0000000000000000
Dcache Par Err Stat Reg x0000000000000000
Virtual Address Reg xFFFFFFFF80248000
Memory Mgmt Flt Sts Reg x0000000000014450
If Err, Reference Resulted in DTB Miss
Fault Inst RA Field: x0000000000000011
Fault Inst Opcode: x0000000000000028
Scache Address Reg xFFFFFF000001914F
Scache Status Reg x0000000000000000
Bcache Tag Address Reg xFFFFFF80000FBFFF
Last Bcache Access Resulted in a Hit.
Value of Parity Bit for Tag Control Status
Bits Dirty, Shared & Valid is Set.
Value of Tag Control Dirty Bit is Clear.
Value of Tag Control Shared Bit is Set.
Value of Tag Control Valid Bit is Set.
Value of Parity Bit Covering Tag Store
Address Bits is Set.
Tag Address<38:20> Is: x0000000000000000
Ext Interface Address Reg xFFFFFF839200001F
Fill Syndrome Reg x0000000000000007
Ext Interface Status Reg xFFFFFFF004FFFFFF
Error Occurred During D-ref Fill
LD LOCK xFFFFFF000060340F
- SYSTEM SPECIFIC REGS -
Configuration Reg (R0) x380003F238000002
LOW LONGWORD Slice Follows
RATTLER Gate Array: Revision #2
Bit 12 Clr: Cmd/Data NOACK are Errors
Bit 24 Clr: IDLEBC Assert in Last Cycle 4
Bit 25 Clr: IDLEBC Assert During Cycle 4
Bit 27 Set: ACK Set_Dirty & Set_Lock Cmds
CACHE Size Field: 4 MB Cache
HIGH LONGWORD Slice Follows
RATTLER Gate Array: Revision #2
Bit 36 Set: Rx IPL31 on CBus CERR Assert
Bit 37 Set: Rx HALT on CBus SYS_EVENT
Bit 38 Set: Rx HALT on IIRR CSR24 HALT Req
Bit 39 Set: Rx INTERPROC INT on Write to
IIRR CSR24 INTERPROC INT Req
Bit 40 Set: Enable CIRQ<0> INT From T2
Bit 41 Set: Enable CIRQ<1> INT From XIO
Bit 44 Clr: Cmd/Data NOACK are Errors
Bit 56 Clr: IDLEBC Assert in Last Cycle 4
Bit 57 Clr: IDLEBC Assert During Cycle 4
Bit 59 Set: ACK Set_Dirty & Set_Lock Cmds
CACHE Size Field: 4 MB Cache
Error Summary Reg (R1) x0000000000000000
EVB Control Register (R2) x0000006100000061
LOW LONGWORD Slice Follows
Bit 0 Set: Enable Addr-Cmd Parity Checking
Bit 5 Set: Enable Bcache ECC Corr QW0/QW2
Bit 6 Set: Enable ECC Check - QW0/QW2 Data
HIGH LONGWORD Slice Follows
Bit 32 Set: Enable Addr-Cmd Parity Check
Bit 37 Set: Enable Bcache ECC Corr QW1/QW3
Bit 38 Set: Enable ECC Check-QW1/QW3 Data
Victim Error Addr (R3) x01CEC00601CEC006
LOW LONGWORD Slice Follows
EVB<33:4> Victim Addr x0000000001CEC006
HIGH LONGWORD Slice Follows
EVB<33:4> Victim Addr x0000000001CEC006
Correctable Err Reg (R4) x0000000000000000
LOW LONGWORD Slice Follows
QW0 ECC Syndrome: No Syndrome Bits Set
QW2 ECC Syndrome: No Syndrome Bits Set
HIGH LONGWORD Slice Follows
QW1 ECC Syndrome: No Syndrome Bits Set
QW3 ECC Syndrome: No Syndrome Bits Set
Correctable Err Addr (R5) xB800000AB800000A
LOW LONGWORD Slice Follows
Bit 32 Set: EV-Bus Bit 39, IO Bit, Set
EVB<34:4> Corr Err Adr x000000005800000A
HIGH LONGWORD Slice Follows
Bit 63 Set: EV-Bus Bit 39, IO Bit, Set
EVB<34:4> Corr Err Adr x000000005800000A
Uncorrectable Error (R6) x8000000080000000
LOW LONGWORD Slice Follows
EVB<3:0> CMD: Command Field = x8
QW0 Uncorr ECC Syndrome x0000000000000000
QW2 Uncorr ECC Syndrome x0000000000000000
HIGH LONGWORD Slice Follows
EVB<3:0> CMD: Command Field = x8
QW1 Uncorr ECC Syndrome x0000000000000000
QW3 Uncorr ECC Syndrome x0000000000000000
Uncorrectable Err Adr(R7) xB800000EB800000E
LOW LONGWORD Slice Follows
Bit 32 Set: EV-Bus Bit 39, IO Bit, Set
EVB<34:4> Uncor Err Adr x000000005800000E
HIGH LONGWORD Slice Follows
Bit 63 Set: EV-Bus Bit 39, IO Bit, Set
EVB<34:4> Uncor Err Adr x000000005800000E
EVB Reserve Register (R8) x0000000000000000
Duplicate Tag Control(R9) x0000011100000111
LOW LONGWORD Slice Follows
Bit 0 Set: Duplicate Tag Enable
Bit 4 Set: Enable Tag Ctrl Parity Checking
Bit 8 Set: Enable Tag Parity Checking
HIGH LONGWORD Slice Follows
Bit 32 Set: Duplicate Tag Enable
Bit 36 Set: Enable Tag Ctl Parity Checking
Bit 40 Set: Enable Tag Parity Checking
Duplicate Tag Error (R10) x0000000000E02740
LOW LONGWORD Slice Follows
Dup Tag Store Err Adr x000000000007013A
Dup Tag Test Control(R11) x0000000000000000
LOW LONGWORD Slice Follows
Bit 3 Clr: Write Good Control Store Parity
Bit 31 Clr: Write Good Tag Store Parity
Duplicate Tag Address x0000000000000000
MUX'ed Tag/Addr Field x0000000000000000
Partial Tag Field x0000000000000000
Duplicate Tag Test (R12) x8180000D8180000D
LOW LONGWORD Slice Follows
Bit 0 Set: Duplicate Tag Dirty Bit
Bit 2 Set: Duplicate Tag Valid Bit
Bit 3 Set: TAG Control Parity Bit
Bit 31 Set: Dup Tag RAM, TAG Parity Bit
Dup Tag RAM, TAG Data x0000000000000018
HIGH LONGWORD Slice Follows
Bit 32 Set: Duplicate Tag Dirty Bit
Bit 34 Set: Duplicate Tag Valid Bit
Bit 35 Set: TAG Control Parity Bit
Bit 63 Set: Dup Tag RAM, TAG Parity Bit
Dup Tag RAM, TAG Data x0000000000000018
Dup Tag Reserve Reg (R13) x0000000000000000
I-Bus Control Stat (R14) x0000100000001000
LOW LONGWORD Slice Follows
Bit 12 Set: Enable I-Bus Parity Check
HIGH LONGWORD Slice Follows
Bit 44 Set: Enable I-Bus Parity Check
I-Bus Error Addr Reg(R15) x4F201CEFE0000073
LOW LONGWORD Slice Follows
C-Bus<31:0> C/A Data x00000000E0000073
HIGH LONGWORD Slice Follows
C-Bus<63:32> C/A Data x000000004F201CEF
Arbitration Ctrl Reg(R16) x0000012000000120
LOW LONGWORD Slice Follows
Bit 5 Set: C-Bus2 DONATE Mode Enabled
Bit 8 Set: C-Bus2 PAWN Mode Enabled
HIGH LONGWORD Slice Follows
Bit 37 Set: C-Bus2 DONATE Mode Enabled
Bit 40 Set: C-Bus2 PAWN Mode Enabled
C-Bus2 Control Reg (R17) x0000110100001001
LOW LONGWORD Slice Follows
Bit 0 Set: C-Bus2 Parity Checking Enabled
Bit 12 Set: Enable C-Bus2 Error Interrupt
HIGH LONGWORD Slice Follows
Bit 32 Set: C-Bus2 Parity Checking Enabled
CPU Cmdr ID Field: C-Bus2 CPU #0 ID
Bit 44 Set: Enable C-Bus2 Error Interrupt
C-Bus2 Error Reg (R18) x0000000000000000
C-Bus2 Err Addr Low (R19) x4F201CEFE0000093
LOW LONGWORD Slice Follows
CBus CAD<31:0> Er Adr x00000000E0000093
HIGH LONGWORD Slice Follows
CBus CAD<95:64> Er Adr x000000004F201CEF
C-Bus2 Err Addr High(R20) x0F201CEFE000009B
LOW LONGWORD Slice Follows
CBus CAD<63:32> Er Adr x00000000E000009B
HIGH LONGWORD Slice Follows
CBus CAD<127:96> Er Adr x000000000F201CEF
C-Bus2 Reserve Reg (R21) x0000000000000000
Address Lock Reg (R22) x0060340100603401
LOW LONGWORD Slice Follows
Bit 0 Set: Lock Address Field Valid
EV<30:5> Lock Address x00000000000301A0
HIGH LONGWORD Slice Follows
Bit 32 Set: Lock Address Field Valid
EV<30:5> Lock Address x00000000000301A0
Proc Mailbox Reg (R23) x0000000000000000
Inter-Proc Int Req (R24) x0001000000000000
HIGH LONGWORD Slice Follows
Bit 48 Set: Interprocessor Interrupt
System Int Clear Reg(R25) x0011001000000000
HIGH LONGWORD Slice Follows
Bit 36 Set: Interval Timer INT State
Bit 48 Set: Interprocessor Interrupt State
Bit 52 Set: State of CIRQ<0> from T2
Perf Monitor Ctl Reg(R26) x0000000000000000
Perf Monitor Reg 1 (R27) x0000000000000000
Perf Monitor Reg 2 (R28) x0000000000000000
Perf Monitor Reg 3 (R29) x0000000000000000
Perf Monitor Reg 4 (R30) x0000000000000000
Perf Monitor Reg 5 (R31) x0000000000000000
-- ENTRY FRAME FOLLOWS --
Frame ID x00000011 T2 System-Bus to PCI Bridge Frame
IO Control/Status Reg xFE000003230605F0
Bit 4 Set: PCI Slot 0 Present
Bit 5 Set: PCI Slot 0 Present
Bit 6 Set: PCI Interrupt Detected
Bit 7 Set: TLB Error Checking Enabled
Bit 8 Set: CBUS CXACK Check Enabled
Bit 10 Set: EV5 Exclusive Exchange Enabled
Bit 18 Set: PCI Slot 1 Present
Bit 24 Set: NOACK, CUCERR, OutOfSync Enbld
Bit 25 Set: PCI Memory Space Enabled
Bit 29 Set: CBUS Parity Checking Enabled
Bit 32 Set: CBUS Back-to-Back Cycles Enbld
T2 Revision: Pass 2
State Machine Vis Select: CBUS Cyc Counter
Bit 57 Set: PCI NMI Interrupts Enabled
Bit 58 Set: PCI Dev Timeout Inter Enabled
Bit 59 Set: PCI SERR# Interrupts Enabled
Bit 60 Set: PCI PERR# Interrupts Enabled
Bit 61 Set: PCI Rd Data Prty Inter Enabled
Bit 62 Set: PCI Adr Parity Inter Enabled
Bit 63 Set: PCI Wrt Data Prty Inter Enbled
CERR1 CBUS Error Reg 1 x0000000000040000
Bit 18 Set: Invalid PFN Error
CERR2 Failed C/A <63:00> x0040359800403598
CERR3 Failed C/A <127:64> xF083FFFFF083FFFF
PERR1 PCI Error Reg 1 x0000000000000000
PERR2 PCI Cmd & Err Addr x00000007000B8EFC
Failed Cmd & Addr Valid When Parity Error
Failed PCI Cmd: x7 Memory Write
PCI Error Address: x00000000000B8EFC
HAE0_1 High Adr Ext Reg 1 x0000000000000010
HAE0_1 <4:0> is Sparse Mem PCI_AD <31:27>
HAE0_2 High Adr Ext Reg 2 x0000000000000000
HBASE PC Hole Base Reg x000000000010603F
PC Hole End Addr: x000000000000003F
Bit 13 Set: PC Hole Enable 1
Bit 14 Set: PC Hole Enable 2
PC Hole Start Addr: x0000000000000020
WBASE1 Window Base Reg 1 x00000000400807FF
PCI Window End Adr: x00000000000007FF
Bit 19 Set: PCI Window Enable
PCI Window Start Adr: x0000000000000400
WMASK1 Window Mask Reg 1 x000000003FF00000
PCI Window Mask: x00000000000003FF
TBASE1 Translated Base R1 x0000000000000000
Translated Base Addr: x0000000000000000
WBASE2 Window Base Reg 2 x00000000000C03FF
PCI Window End Adr: x00000000000003FF
Bit 18 Set: Scatter-Gather Enable
Bit 19 Set: PCI Window Enable
PCI Window Start Adr: x0000000000000000
WMASK2 Window Mask Reg 2 x000000003FF00000
PCI Window Mask: x00000000000003FF
TBASE2 Translated Base R2 x0000000000800000
Translated Base Addr: x0000000000004000
TDR0 TLB Data Register 0 x0000000000000000
TDR0 Data is Invalid
TLB Entry 0 Tag Data x0000000000000000
TLB Entry 0 PFN Data x0000000000000000
TDR1 TLB Data Register 1 x0000000000000000
TDR1 Data is Invalid
TLB Entry 1 Tag Data x0000000000000000
TLB Entry 1 PFN Data x0000000000000000
TDR2 TLB Data Register 2 x0000000000000000
TDR2 Data is Invalid
TLB Entry 2 Tag Data x0000000000000000
TLB Entry 2 PFN Data x0000000000000000
TDR3 TLB Data Register 3 x0000000000000000
TDR3 Data is Invalid
TLB Entry 3 Tag Data x0000000000000000
TLB Entry 3 PFN Data x0000000000000000
TDR4 TLB Data Register 4 x0000000000000000
TDR4 Data is Invalid
TLB Entry 4 Tag Data x0000000000000000
TLB Entry 4 PFN Data x0000000000000000
TDR5 TLB Data Register 5 x0000000000000000
TDR5 Data is Invalid
TLB Entry 5 Tag Data x0000000000000000
TLB Entry 5 PFN Data x0000000000000000
TDR6 TLB Data Register 6 x0000000000000000
TDR6 Data is Invalid
TLB Entry 6 Tag Data x0000000000000000
TLB Entry 6 PFN Data x0000000000000000
TDR7 TLB Data Register 7 x0000000000000000
TDR7 Data is Invalid
TLB Entry 7 Tag Data x0000000000000000
TLB Entry 7 PFN Data x0000000000000000
-- ENTRY FRAME FOLLOWS --
Frame ID x00000008 Memory Frame
Memory Module ID x00000000
Error Register 1 x0000000000000000
Command Trap Register 1 xE2000008E2000008
Command Trap Register 2 x00201CEF40201CEF
Configuration Register x8001506880015068
EDC Status Register 1 x000A0A4306CF00E4
[Even] Read CBITS <11:0> x00000000000000E4
[Even] Write CBITS <11:0> x00000000000006CF
[Odd] Read CBITS <11:0> x0000000000000A43
[Odd] Write CBITS <11:0> x000000000000000A
EDC Status Register 2 x000000170000000D
[Even] Syndrome <11:0> x000000000000000D
[Odd] Syndrome <11:0> x0000000000000017
EDC Control Register x2000000020000000
[Even] Substitute Read Cbits Used
[Even] Substitute Write Cbits Used
[Even] Disable Inbound Parity Check
[Even] Enable EDC swap Mode
[Even] Complement Read Data Parity
[Even] Disable EDC Correction
[Even] Disable EDC Reporting
[Odd] Substitute Read Cbits Used
[Odd] Substitute Write Cbits Used
[Odd] Disable Inbound Parity Check
[Odd] Enable EDC swap Mode
[Odd] Complement Read Data Parity
[Odd] Disable EDC Correction
[Odd] Disable EDC Reporting
[Even] Subs. Read CBITS < x0000000000000000
[Even] Subs. Write CBITS x0000000000000000
[Odd] Subs. Read CBITS <1 x0000000000000000
[Odd] Subs. Write CBITS < x0000000000000000
Stream Buffer Control Reg x0000080000000800
Refresh Control Register x000001D8000001D8
[Even] Refresh Enable
[Odd] Refresh Enable
[Even] Syndrome Mask <11: x00000000000000D8
[Odd] Syndrome Mask <11:0 x00000000000000D8
Filter Control Register x0000000000000000
[Even] Syndrome Mask <11: x0000000000000000
[Even] Bank Select x0000000000000000
[Odd] Syndrome Mask <11:0 x0000000000000000
[Odd] Bank Select x0000000000000000
-- ENTRY FRAME FOLLOWS --
Frame ID x00000008 Memory Frame
Memory Module ID x00000001
NULL Memory Frame. The registers in this
frame contain zeros
-- ENTRY FRAME FOLLOWS --
Frame ID x00000008 Memory Frame
Memory Module ID x00000002
NULL Memory Frame. The registers in this
frame contain zeros
-- ENTRY FRAME FOLLOWS --
Frame ID x00000008 Memory Frame
Memory Module ID x00000003
NULL Memory Frame. The registers in this
frame contain zeros
-- ENTRY FRAME FOLLOWS --
Frame ID x00000000 End Frame
******************************** ENTRY 5 ********************************
Logging OS 2. Digital UNIX
System Architecture 2. Alpha
Event sequence number 6.
Timestamp of occurrence 29-SEP-1998 04:22:42
Host name panda
System type register x00000009 AlphaServer 2x00
Number of CPUs (mpnum) x00000002
CPU logging event (mperr) x00000000
Event validity 1. O/S claims event is valid
Event severity 1. Severe Priority
Entry type 100. CPU Machine Check Errors
CPU Minor class 2. 660 Entry
-- ENTRY FRAME FOLLOWS --
Frame ID x00000022 Machine Check Frame
CPU Number Logging Event 0.
- ALPHA EV5 COMMON REGS -
Flags: x00000000
Machine Check Error Code x00000203 System Detected Uncorr ECC Error
PAL SHADOW REG 0 x0000000000000000
PAL SHADOW REG 1 x0000000000000000
PAL SHADOW REG 2 x0000000000000000
PAL SHADOW REG 3 x0000000000000000
PAL SHADOW REG 4 x0000000000000000
PAL SHADOW REG 5 x0000000000000000
PAL SHADOW REG 6 x0000000000000000
PAL SHADOW REG 7 x0000000000000000
PALTEMP0 x0000000000000007
PALTEMP1 x0000000000000000
PALTEMP2 xFFFFFC0000482280
PALTEMP3 x0000000000004200
PALTEMP4 x000000000171F3C0
PALTEMP5 x0050001800000017
PALTEMP6 x0000000000000019
PALTEMP7 xFFFFFC0000481BA0
PALTEMP8 x1F1E161514020100
PALTEMP9 xFFFFFC0000481FC0
PALTEMP10 xFFFFFC0000556790
PALTEMP11 xFFFFFC0000481E20
PALTEMP12 xFFFFFC00004821F0
PALTEMP13 x0000012000000120
PALTEMP14 x0000000000000001
PALTEMP15 x0000000000000000
PALTEMP16 x0000020306600001
PALTEMP17 x0000000000000000
PALTEMP18 x0000000000000000
PALTEMP19 xFFFFFFFFA048F9D8
PALTEMP20 x000000000077A000
PALTEMP21 xFFFFFC0000482220
PALTEMP22 xFFFFFC0000603300
PALTEMP23 x000000001FC55A38
Exception Address Reg xFFFFFC0000556790
Native-mode Instruction
Exception PC x3FFFFF00001559E4
Exception Summary Reg x0000000000000000
Exception Mask Reg x0000000000000000
PAL Base Address Reg x0000000000014000
Base Addr for PALcode: x0000000000000005
Interrupt Summary Reg x0000000080C00000
External HW Interrupt at IPL22
External HW Interrupt at IPL23
External HW Intr. Machine Check(IPL31)
AST Requests 3-0: x0000000000000000
IBOX Ctrl and Status Reg x0000004160800000
Timeout Counter Bit Clear.
IBOX Timeout Counter Enabled.
Floating Point Instructions will Cause
FEN Exceptions.
PAL Shadow Registers Enabled.
Correctable Error Interrupts Enabled.
ICACHE BIST (Self Test) Was Successful.
Icache Par Err Stat Reg x0000000000000000
Dcache Par Err Stat Reg x0000000000000000
Virtual Address Reg xFFFFFFFF80248000
Memory Mgmt Flt Sts Reg x0000000000014450
If Err, Reference Resulted in DTB Miss
Fault Inst RA Field: x0000000000000011
Fault Inst Opcode: x0000000000000028
Scache Address Reg xFFFFFF000001918F
Scache Status Reg x0000000000000000
Bcache Tag Address Reg xFFFFFF80000FBFFF
Last Bcache Access Resulted in a Hit.
Value of Parity Bit for Tag Control Status
Bits Dirty, Shared & Valid is Set.
Value of Tag Control Dirty Bit is Clear.
Value of Tag Control Shared Bit is Set.
Value of Tag Control Valid Bit is Set.
Value of Parity Bit Covering Tag Store
Address Bits is Set.
Tag Address<38:20> Is: x0000000000000000
Ext Interface Address Reg xFFFFFF839200001F
Fill Syndrome Reg x0000000000000007
Ext Interface Status Reg xFFFFFFF004FFFFFF
Error Occurred During D-ref Fill
LD LOCK xFFFFFF00006033DF
- SYSTEM SPECIFIC REGS -
Configuration Reg (R0) x380003F238000002
LOW LONGWORD Slice Follows
RATTLER Gate Array: Revision #2
Bit 12 Clr: Cmd/Data NOACK are Errors
Bit 24 Clr: IDLEBC Assert in Last Cycle 4
Bit 25 Clr: IDLEBC Assert During Cycle 4
Bit 27 Set: ACK Set_Dirty & Set_Lock Cmds
CACHE Size Field: 4 MB Cache
HIGH LONGWORD Slice Follows
RATTLER Gate Array: Revision #2
Bit 36 Set: Rx IPL31 on CBus CERR Assert
Bit 37 Set: Rx HALT on CBus SYS_EVENT
Bit 38 Set: Rx HALT on IIRR CSR24 HALT Req
Bit 39 Set: Rx INTERPROC INT on Write to
IIRR CSR24 INTERPROC INT Req
Bit 40 Set: Enable CIRQ<0> INT From T2
Bit 41 Set: Enable CIRQ<1> INT From XIO
Bit 44 Clr: Cmd/Data NOACK are Errors
Bit 56 Clr: IDLEBC Assert in Last Cycle 4
Bit 57 Clr: IDLEBC Assert During Cycle 4
Bit 59 Set: ACK Set_Dirty & Set_Lock Cmds
CACHE Size Field: 4 MB Cache
Error Summary Reg (R1) x0000000000000000
EVB Control Register (R2) x0000006100000061
LOW LONGWORD Slice Follows
Bit 0 Set: Enable Addr-Cmd Parity Checking
Bit 5 Set: Enable Bcache ECC Corr QW0/QW2
Bit 6 Set: Enable ECC Check - QW0/QW2 Data
HIGH LONGWORD Slice Follows
Bit 32 Set: Enable Addr-Cmd Parity Check
Bit 37 Set: Enable Bcache ECC Corr QW1/QW3
Bit 38 Set: Enable ECC Check-QW1/QW3 Data
Victim Error Addr (R3) x00E8000600E80006
LOW LONGWORD Slice Follows
EVB<33:4> Victim Addr x0000000000E80006
HIGH LONGWORD Slice Follows
EVB<33:4> Victim Addr x0000000000E80006
Correctable Err Reg (R4) x0000000000000000
LOW LONGWORD Slice Follows
QW0 ECC Syndrome: No Syndrome Bits Set
QW2 ECC Syndrome: No Syndrome Bits Set
HIGH LONGWORD Slice Follows
QW1 ECC Syndrome: No Syndrome Bits Set
QW3 ECC Syndrome: No Syndrome Bits Set
Correctable Err Addr (R5) xB800000AB800000A
LOW LONGWORD Slice Follows
Bit 32 Set: EV-Bus Bit 39, IO Bit, Set
EVB<34:4> Corr Err Adr x000000005800000A
HIGH LONGWORD Slice Follows
Bit 63 Set: EV-Bus Bit 39, IO Bit, Set
EVB<34:4> Corr Err Adr x000000005800000A
Uncorrectable Error (R6) x8000000080000000
LOW LONGWORD Slice Follows
EVB<3:0> CMD: Command Field = x8
QW0 Uncorr ECC Syndrome x0000000000000000
QW2 Uncorr ECC Syndrome x0000000000000000
HIGH LONGWORD Slice Follows
EVB<3:0> CMD: Command Field = x8
QW1 Uncorr ECC Syndrome x0000000000000000
QW3 Uncorr ECC Syndrome x0000000000000000
Uncorrectable Err Adr(R7) xB800000EB800000E
LOW LONGWORD Slice Follows
Bit 32 Set: EV-Bus Bit 39, IO Bit, Set
EVB<34:4> Uncor Err Adr x000000005800000E
HIGH LONGWORD Slice Follows
Bit 63 Set: EV-Bus Bit 39, IO Bit, Set
EVB<34:4> Uncor Err Adr x000000005800000E
EVB Reserve Register (R8) x0000000000000000
Duplicate Tag Control(R9) x0000011100000111
LOW LONGWORD Slice Follows
Bit 0 Set: Duplicate Tag Enable
Bit 4 Set: Enable Tag Ctrl Parity Checking
Bit 8 Set: Enable Tag Parity Checking
HIGH LONGWORD Slice Follows
Bit 32 Set: Duplicate Tag Enable
Bit 36 Set: Enable Tag Ctl Parity Checking
Bit 40 Set: Enable Tag Parity Checking
Duplicate Tag Error (R10) x0000000000001DA0
LOW LONGWORD Slice Follows
Dup Tag Store Err Adr x00000000000000ED
Dup Tag Test Control(R11) x0000000000000000
LOW LONGWORD Slice Follows
Bit 3 Clr: Write Good Control Store Parity
Bit 31 Clr: Write Good Tag Store Parity
Duplicate Tag Address x0000000000000000
MUX'ed Tag/Addr Field x0000000000000000
Partial Tag Field x0000000000000000
Duplicate Tag Test (R12) x19C0000419C00004
LOW LONGWORD Slice Follows
Bit 2 Set: Duplicate Tag Valid Bit
Dup Tag RAM, TAG Data x000000000000019C
HIGH LONGWORD Slice Follows
Bit 34 Set: Duplicate Tag Valid Bit
Dup Tag RAM, TAG Data x000000000000019C
Dup Tag Reserve Reg (R13) x0000000000000000
I-Bus Control Stat (R14) x0000100000001000
LOW LONGWORD Slice Follows
Bit 12 Set: Enable I-Bus Parity Check
HIGH LONGWORD Slice Follows
Bit 44 Set: Enable I-Bus Parity Check
I-Bus Error Addr Reg(R15) xFF83FFFF004036D7
LOW LONGWORD Slice Follows
C-Bus<31:0> C/A Data x00000000004036D7
HIGH LONGWORD Slice Follows
C-Bus<63:32> C/A Data x00000000FF83FFFF
Arbitration Ctrl Reg(R16) x0000012000000120
LOW LONGWORD Slice Follows
Bit 5 Set: C-Bus2 DONATE Mode Enabled
Bit 8 Set: C-Bus2 PAWN Mode Enabled
HIGH LONGWORD Slice Follows
Bit 37 Set: C-Bus2 DONATE Mode Enabled
Bit 40 Set: C-Bus2 PAWN Mode Enabled
C-Bus2 Control Reg (R17) x0000110100001001
LOW LONGWORD Slice Follows
Bit 0 Set: C-Bus2 Parity Checking Enabled
Bit 12 Set: Enable C-Bus2 Error Interrupt
HIGH LONGWORD Slice Follows
Bit 32 Set: C-Bus2 Parity Checking Enabled
CPU Cmdr ID Field: C-Bus2 CPU #0 ID
Bit 44 Set: Enable C-Bus2 Error Interrupt
C-Bus2 Error Reg (R18) x0000000000000000
C-Bus2 Err Addr Low (R19) xFF83FFFF004036D7
LOW LONGWORD Slice Follows
CBus CAD<31:0> Er Adr x00000000004036D7
HIGH LONGWORD Slice Follows
CBus CAD<95:64> Er Adr x00000000FF83FFFF
C-Bus2 Err Addr High(R20) xFF9FFFFF00000793
LOW LONGWORD Slice Follows
CBus CAD<63:32> Er Adr x0000000000000793
HIGH LONGWORD Slice Follows
CBus CAD<127:96> Er Adr x00000000FF9FFFFF
C-Bus2 Reserve Reg (R21) x0000000000000000
Address Lock Reg (R22) x006033C0006033C0
LOW LONGWORD Slice Follows
EV<30:5> Lock Address x000000000003019E
HIGH LONGWORD Slice Follows
EV<30:5> Lock Address x000000000003019E
Proc Mailbox Reg (R23) x0000000000000000
Inter-Proc Int Req (R24) x0001000000000000
HIGH LONGWORD Slice Follows
Bit 48 Set: Interprocessor Interrupt
System Int Clear Reg(R25) x0001001100000000
HIGH LONGWORD Slice Follows
Bit 32 Set: C-Bus2 Error Interrupt State
Bit 36 Set: Interval Timer INT State
Bit 48 Set: Interprocessor Interrupt State
Perf Monitor Ctl Reg(R26) x0000000000000000
Perf Monitor Reg 1 (R27) x0000000000000000
Perf Monitor Reg 2 (R28) x0000000000000000
Perf Monitor Reg 3 (R29) x0000000000000000
Perf Monitor Reg 4 (R30) x0000000000000000
Perf Monitor Reg 5 (R31) x0000000000000000
-- ENTRY FRAME FOLLOWS --
Frame ID x00000011 T2 System-Bus to PCI Bridge Frame
IO Control/Status Reg xFE000003230605B0
Bit 4 Set: PCI Slot 0 Present
Bit 5 Set: PCI Slot 0 Present
Bit 7 Set: TLB Error Checking Enabled
Bit 8 Set: CBUS CXACK Check Enabled
Bit 10 Set: EV5 Exclusive Exchange Enabled
Bit 18 Set: PCI Slot 1 Present
Bit 24 Set: NOACK, CUCERR, OutOfSync Enbld
Bit 25 Set: PCI Memory Space Enabled
Bit 29 Set: CBUS Parity Checking Enabled
Bit 32 Set: CBUS Back-to-Back Cycles Enbld
T2 Revision: Pass 2
State Machine Vis Select: CBUS Cyc Counter
Bit 57 Set: PCI NMI Interrupts Enabled
Bit 58 Set: PCI Dev Timeout Inter Enabled
Bit 59 Set: PCI SERR# Interrupts Enabled
Bit 60 Set: PCI PERR# Interrupts Enabled
Bit 61 Set: PCI Rd Data Prty Inter Enabled
Bit 62 Set: PCI Adr Parity Inter Enabled
Bit 63 Set: PCI Wrt Data Prty Inter Enbled
CERR1 CBUS Error Reg 1 x0000000000040000
Bit 18 Set: Invalid PFN Error
CERR2 Failed C/A <63:00> x0040359800403598
CERR3 Failed C/A <127:64> xF083FFFFF083FFFF
PERR1 PCI Error Reg 1 x0000000000000000
PERR2 PCI Cmd & Err Addr x00000007036D60E0
Failed Cmd & Addr Valid When Parity Error
Failed PCI Cmd: x7 Memory Write
PCI Error Address: x00000000036D60E0
HAE0_1 High Adr Ext Reg 1 x0000000000000010
HAE0_1 <4:0> is Sparse Mem PCI_AD <31:27>
HAE0_2 High Adr Ext Reg 2 x0000000000000000
HBASE PC Hole Base Reg x000000000010603F
PC Hole End Addr: x000000000000003F
Bit 13 Set: PC Hole Enable 1
Bit 14 Set: PC Hole Enable 2
PC Hole Start Addr: x0000000000000020
WBASE1 Window Base Reg 1 x00000000400807FF
PCI Window End Adr: x00000000000007FF
Bit 19 Set: PCI Window Enable
PCI Window Start Adr: x0000000000000400
WMASK1 Window Mask Reg 1 x000000003FF00000
PCI Window Mask: x00000000000003FF
TBASE1 Translated Base R1 x0000000000000000
Translated Base Addr: x0000000000000000
WBASE2 Window Base Reg 2 x00000000000C03FF
PCI Window End Adr: x00000000000003FF
Bit 18 Set: Scatter-Gather Enable
Bit 19 Set: PCI Window Enable
PCI Window Start Adr: x0000000000000000
WMASK2 Window Mask Reg 2 x000000003FF00000
PCI Window Mask: x00000000000003FF
TBASE2 Translated Base R2 x0000000000800000
Translated Base Addr: x0000000000004000
TDR0 TLB Data Register 0 x0000000000000000
TDR0 Data is Invalid
TLB Entry 0 Tag Data x0000000000000000
TLB Entry 0 PFN Data x0000000000000000
TDR1 TLB Data Register 1 x0000000000000000
TDR1 Data is Invalid
TLB Entry 1 Tag Data x0000000000000000
TLB Entry 1 PFN Data x0000000000000000
TDR2 TLB Data Register 2 x0000000000000000
TDR2 Data is Invalid
TLB Entry 2 Tag Data x0000000000000000
TLB Entry 2 PFN Data x0000000000000000
TDR3 TLB Data Register 3 x0000000000000000
TDR3 Data is Invalid
TLB Entry 3 Tag Data x0000000000000000
TLB Entry 3 PFN Data x0000000000000000
TDR4 TLB Data Register 4 x0000000000000000
TDR4 Data is Invalid
TLB Entry 4 Tag Data x0000000000000000
TLB Entry 4 PFN Data x0000000000000000
TDR5 TLB Data Register 5 x0000000000000000
TDR5 Data is Invalid
TLB Entry 5 Tag Data x0000000000000000
TLB Entry 5 PFN Data x0000000000000000
TDR6 TLB Data Register 6 x0000000000000000
TDR6 Data is Invalid
TLB Entry 6 Tag Data x0000000000000000
TLB Entry 6 PFN Data x0000000000000000
TDR7 TLB Data Register 7 x0000000000000000
TDR7 Data is Invalid
TLB Entry 7 Tag Data x0000000000000000
TLB Entry 7 PFN Data x0000000000000000
-- ENTRY FRAME FOLLOWS --
Frame ID x00000008 Memory Frame
Memory Module ID x00000000
Error Register 1 x0000000000000000
Command Trap Register 1 xE2000008E2000008
Command Trap Register 2 x0020114740201147
Configuration Register x8001506880015068
EDC Status Register 1 x08BC0C1409090C14
[Even] Read CBITS <11:0> x0000000000000C14
[Even] Write CBITS <11:0> x0000000000000909
[Odd] Read CBITS <11:0> x0000000000000C14
[Odd] Write CBITS <11:0> x00000000000008BC
EDC Status Register 2 x000000170000000D
[Even] Syndrome <11:0> x000000000000000D
[Odd] Syndrome <11:0> x0000000000000017
EDC Control Register x2000000020000000
[Even] Substitute Read Cbits Used
[Even] Substitute Write Cbits Used
[Even] Disable Inbound Parity Check
[Even] Enable EDC swap Mode
[Even] Complement Read Data Parity
[Even] Disable EDC Correction
[Even] Disable EDC Reporting
[Odd] Substitute Read Cbits Used
[Odd] Substitute Write Cbits Used
[Odd] Disable Inbound Parity Check
[Odd] Enable EDC swap Mode
[Odd] Complement Read Data Parity
[Odd] Disable EDC Correction
[Odd] Disable EDC Reporting
[Even] Subs. Read CBITS < x0000000000000000
[Even] Subs. Write CBITS x0000000000000000
[Odd] Subs. Read CBITS <1 x0000000000000000
[Odd] Subs. Write CBITS < x0000000000000000
Stream Buffer Control Reg x0000080000000800
Refresh Control Register x000001D8000001D8
[Even] Refresh Enable
[Odd] Refresh Enable
[Even] Syndrome Mask <11: x00000000000000D8
[Odd] Syndrome Mask <11:0 x00000000000000D8
Filter Control Register x0000000000000000
[Even] Syndrome Mask <11: x0000000000000000
[Even] Bank Select x0000000000000000
[Odd] Syndrome Mask <11:0 x0000000000000000
[Odd] Bank Select x0000000000000000
-- ENTRY FRAME FOLLOWS --
Frame ID x00000008 Memory Frame
Memory Module ID x00000001
NULL Memory Frame. The registers in this
frame contain zeros
-- ENTRY FRAME FOLLOWS --
Frame ID x00000008 Memory Frame
Memory Module ID x00000002
NULL Memory Frame. The registers in this
frame contain zeros
-- ENTRY FRAME FOLLOWS --
Frame ID x00000008 Memory Frame
Memory Module ID x00000003
NULL Memory Frame. The registers in this
frame contain zeros
-- ENTRY FRAME FOLLOWS --
Frame ID x00000000 End Frame
Received on Tue Oct 13 1998 - 12:49:04 NZDT