Hello,
Uerf is reporting me a CPU Exception, no panics, my computer is an
AlphaServer
2100, 512MB ( 4-128MB modules ), dual alpha 190Mhz, StorageWorks Raid
Array
200, with Raid EISA Host Adapter
SRM console shows no error for any FRU ( show fru, show error...).
Below are the output of uerf and dia.
From dia I obtained the following:
"CPU Minor class 2. 660 Entry"
it means a system detected error external to CPU. Probably ( surely )
CPU is not the culprit, in my opinion and the following:
"Memory Module ID x00000000
Error Register 1 x0004000100000000
[Odd] Error Summary
[Odd] EDC Corr Error"
And error detected and corrected on Memory module 0, my first 128 memory
module,
so this look like the faulty fru.
Below are the complete output of uerf and dia, any comment or idea
will apreciated,
TIA,
Abdon
********************************* ENTRY 1.
*********************************
----- EVENT INFORMATION -----
EVENT CLASS ERROR EVENT
OS EVENT TYPE 100. CPU EXCEPTION
SEQUENCE NUMBER 14.
OPERATING SYSTEM DEC OSF/1
OCCURRED/LOGGED ON Wed May 27 11:23:39 1998
OCCURRED ON SYSTEM cfgos
SYSTEM ID x00020009 CPU TYPE: DEC 2100
SYSTYPE x00000000
PROCESSOR COUNT 2.
PROCESSOR WHO LOGGED x00000001
----- UNIT INFORMATION -----
UNIT CLASS CPU
DECevent V2.2
******************************** ENTRY 1
********************************
Logging OS 2. Digital UNIX
System Architecture 2. Alpha
Event sequence number 14.
Timestamp of occurrence 27-MAY-1998 11:23:39
Host name cfgos
System type register x00000009 AlphaServer 2x00
Number of CPUs (mpnum) x00000002
CPU logging event (mperr) x00000001
Event validity 1. O/S claims event is valid
Event severity 1. Severe Priority
Entry type 100. CPU Machine Check Errors
CPU Minor class 2. 660 Entry
-- ENTRY FRAME FOLLOWS --
Frame ID x00000002 Machine Check Frame
Byte Count x00000220
Byte Count x0220
Processor Specific Offset x00000110
System Specific Offset x000001A0
PAL Error Type Code x0000008A Bugchk Generated by OS specific
PALcode
PAL Frame Revision x00000001
- ALPHA CHIP REGISTERS -
PALTEMP1 x0000000000000000
PALTEMP2 x000002F800000004
PALTEMP3 xFFFFFC00006AD838
PALTEMP4 x0000000000000000
PALTEMP5 x0000000000000001
PALTEMP6 x0000000000000240
PALTEMP7 x0000000000004800
PALTEMP8 x0000000000000600
PALTEMP9 x0000000000000000
PALTEMP10 xFFFFFC00004E48A0
PALTEMP11 x0000000000000000
PALTEMP12 xFFFFFC00004E4C40
PALTEMP13 xFFFFFC00004E4C70
PALTEMP14 xFFFFFC00004E4CD0
PALTEMP15 xFFFFFC00004E4A40
PALTEMP16 xFFFFFC00004E4750
PALTEMP17 x0000000000019330
PALTEMP18 x0000000000000000
PALTEMP19 xFFFFFFFFA0467948
PALTEMP20 xFFFFFC0000660D50
PALTEMP21 xEDCBA987EDCBA987
PALTEMP22 x4042427272727272
PALTEMP23 xBBFFD7FFBFFFABFF
PALTEMP24 x0000000000000000
PALTEMP25 x0000000000010000
PALTEMP26 x0000000000000001
PALTEMP27 x0000000000000001
PALTEMP28 x00000000007CE000
PALTEMP29 xFFFFFFFC00000000
PALTEMP30 x0000000000000001
PALTEMP31 x000000001D015A58
Exception Address Reg xFFFFFC0000478AFC
Exception Address Reg Provides
Information
About The Most Recent Exception.
Address Points to Native-Mode
Instruction
If Machine Check or Math Trap
Exception,
On Return Subtract 4 from Exception
PC.
Last Exception Addr PC:
x3FFFFF000011E2BF
Exception Summary Reg x0000000000000000
Exception Mask Reg x0000000000000000
Icache Ctrl & Status Reg x000002F800000004
Performance Counters Disabled
Empty Wrt Buffer Before Issuing Next
Inst
Branch Prediction Selection: Not Taken
JSR Stack is Disabled
Instructions Can Only Single Issue
If Not in PALmode, Executing Reserved
Inst
Opcode Will Result in OPCDEC
Exception.
Super Page Istream Memory Mapping
Disabled
Float Point Inst Will Cause FEN
Exception
Icache Addr Space Numb:
x0000000000000000
PALcode Base Address Reg x0000000000014000
PALcode Base Address:
x0000000000000005
Hardware Int Enable Reg x00000000000004F0
CRD Error Interrupts Enabled
CPU Hrdw Interrupts Enabled Irq_h Pin
0
CPU Hrdw Interrupts Enbld Irq_h Pins
3,4,5
Performance Cntr 0 & 1 Interrupts
Disabled
Serial Line Interrupts Disabled
NO AST Interrupts Enabled In Any Mode
Hardware Int Request Reg x0000000000000042
Any Hrdw Int Req With Companion Enable
Set
NO Softw Int Req With Companion Enable
Set
NO AST Int Req With Companion Enable
Set
CPU Hrdw Interrupt Request on Irq_h
Pin 4
Memory Management CSR x0000000000003640
MMCSR Valid Only on Mem Mgt Err, DTB
Miss,
D-Stream Fault, Dcache Parity
Error.
Last Faulting Instruction RA Field: R4
Last Faulting Instruction Opcode
Follows:
x1B - Reserved for PALcode
(Data) Cache Status Reg x0000000000000007
This is EV4 Data Cache Status
Reg(DC_STAT)
EV4 Chip is Production Version of
21064
Last Load or Store Missed Dcache
Cache Address Reg x00000007FFFFFFFF
Abox Control Reg x000000000000142E
Machine Checks Enabled for Uncorr
Errors
CRD Interrupts Enabled
Single Entry Icache Stream Buffer
Enabled
Enable Super Page Dstream Virtual Addr
Map
VA<33:13> to PA<33:13>, if
VA<42:41>=2.
Lock Operation Conforms to Alpha
Architect
Dcache Enabled
16K Byte Dcache Selected
Bus Interface Status Reg x0000000000000240
Bus Interface Address Reg x0000000000019330
Address Only Valid if Bus Interface
Status
Register Error Bit 0,1,2, or 3 is
Set.
BIU Addr adr_h <4:2>: x4
BIU Addr adr_h<33:5>:
x0000000000000C99
Bus Interface Control Reg x0000000E30006447
External Cache (Bcache) Enabled
ECC MODE: External Cache ECC Enabled
Cache Rams are Output Enable
Controlled
Ext Cache Rd Access Time: 5 CPU Cycles
Ext Cache Wrt Cycle Time: 5 CPU Cycles
Size of External Cache: 1 Mbyte
Ext Cache Rd Time Controlling Bcache
Reads
Ext Cache Wrt En Ctrl:
x0000000000000003
Fill Syndrome Reg x0000000000000000
No Error in Low Long Word of Quad Word
No Error in Upper Long Word of Quad
Word
Fill Address Reg x0000000000006500
Addr Only Valid if Bus Interface Stat
Reg
ECC(Bit 8) or PARITY(Bit 10) Error
Set.
Cache Blk Phy Adr<33:5>
x0000000000000328
Virtual Address Reg x0000000000006570
Dstream FLT/DTB Miss VA
x0000000000006570
Bcache Tag Reg x86386001CB186860
Last Bcache Access Resulted in a Miss
Parity Bit for Bcache Tag Status Bits
Clr
Bcache Tag Dirty Bit Clear
Bcache Tag Shared Bit Clear
Bcache Tag Valid Bit Clear
Bcache Tag Addrress Parity Bit Clear
Tag Being Probed: x000000000000C343
- SYSTEM SPECIFIC REGS -
Bcache Control Reg (R0) x400001C5400001C5
Bits in LOW LONGWORD SLICE
Follows
Bcache Allocation Enabled on Cacheable
Cyc
Enb Parity Chk Tag Ctrl, Tag Addr, Dup
Tag
Enb Hardware Interrupt for CSR1 EDC
Errors
Enable EDC Correction of Proc Write
Data,
Victim Data, and Dirty Read Hit
Data.
Enb Data Store and Proc Wrt Data EDC
Check
Unconditional Updates of Bcache Will
Occur
Allocation Only on Masked Processor
Writes
Bcache Initialization Disabled
Force EDC/Control Disabled (Bit 12
Clr)
Cache Size: Between 0 to 1MB
Force Following LW0/LW2 EDC, if Bit 12
Set
Forced LW0/LW2 EDC:
x0000000000000000
Bits in HIGH LONGWORD SLICE
Follows
Bcache Allocation Enabled on Cacheable
Cyc
Enb Parity Chk Tag Ctrl, Tag Addr, Dup
Tag
Enb Hardware Interrupt for CSR1 EDC
Errors
Enable EDC Correction of Proc Write
Data,
Victim Data, and Dirty Read Hit
Data.
Enb Data Store and Proc Wrt Data EDC
Check
Unconditional Updates of Bcache Will
Occur
Allocation Only on Masked Processor
Writes
Bcache Initialization Disabled
Force EDC/Control Disabled (Bit 44
Clr)
Cache Size: Between 0 to 1MB
Force Following LW1/LW3 EDC, if Bit 44
Set
Forced LW1/LW3 EDC:
x0000000000000000
Bcache Corr Error (R1) x0000000000000000
Bits in LOW LONGWORD SLICE
Follows
LW0 EDC Syndrome: x0000000000000000
LW2 EDC Syndrome: x0000000000000000
Bits in HIGH LONGWORD SLICE
Follows
LW1 EDC Syndrome: x0000000000000000
LW3 EDC Syndrome: x0000000000000000
Bcache Corr Err Addr (R2) x0000000000000000
Bits in LOW LONGWORD SLICE
Follows
Ctrl Parity Bit CLR - Last Bc Loc
Accessed
Last LW0/LW2 MAP Index:
x0000000000000000
Last LW0/LW2 Tag Field:
x0000000000000000
Bits in HIGH LONGWORD SLICE
Follows
Ctrl Parity Bit CLR - Last Bc Loc
Accessed
Last LW1/LW3 MAP Index:
x0000000000000000
Last LW1/LW3 Tag Field:
x0000000000000000
Bcache Uncorr Error (R3) x0000090000000900
Bits in LOW LONGWORD SLICE
Follows
LW0 EDC Syndrome: x0000000000000000
LW2 EDC Syndrome: x0000000000000000
Bits in HIGH LONGWORD SLICE
Follows
LW1 EDC Syndrome: x0000000000000000
LW3 EDC Syndrome: x0000000000000000
Bcache Uncorr Err Adr(R4) x16700CB716700CB7
Bits in LOW LONGWORD SLICE
Follows
Sys-Bus Last Predicted Tag Parity Bit:
Clr
Tag Parity Bit CLR - Last Bc Loc
Accessed
Last LW0/LW2 MAP Index:
x0000000000000CB7
Last LW0/LW2 Tag Field:
x00000000000002CE
Bits in HIGH LONGWORD SLICE
Follows
Sys-Bus Last Predicted Tag Parity Bit:
Clr
Tag Parity Bit CLR - Last Bc Loc
Accessed
Last LW1/LW3 MAP Index:
x0000000000000CB7
Last LW1/LW3 Tag Field:
x00000000000002CE
Duplicate Tag Err Reg(R5) x0005912800059128
Bits in LOW LONGWORD SLICE
Follows
Last Dup Tag Stor Offst
x000000000000004A
Dup Tag BANK-0 Parity CLR -Last Loc
Access
Dup Tag Stor BANK-0 Tag
x0000000000000164
Dup Tag BANK-1 Parity CLR -Last Loc
Access
Dup Tag Stor BANK-1 Tag
x0000000000000000
Bits in HIGH LONGWORD SLICE
Follows
Last Dup Tag Stor Offst
x000000000000004A
Dup Tag BANK-0 Parity CLR -Last Loc
Access
Dup Tag Stor BANK-0 Tag
x0000000000000164
Dup Tag BANK-1 Parity CLR -Last Loc
Access
Dup Tag Stor BANK-1 Tag
x0000000000000000
System Bus Control (R6) x0000684800006848
Bits in LOW LONGWORD SLICE
Follows
En Parity Check C/A LW0,1 & Data
LW0,2,4,6
Commander ID: CPU1 (CPU Commanding CSR
Rd)
Enable C-Bus Error Interrupts
Second QuadWord Selected for Timing
Config
DRAK<1> Selected for Timing
Configuration
Bits in HIGH LONGWORD SLICE
Follows
En Parity Check C/A LW2,3 & Data
LW1,3,5,7
Commander ID: CPU1 (CPU Commanding CSR
Rd)
Enable C-Bus Error Interrupts
Second QuadWord Selected for Timing
Config
DRAK<1> Selected for Timing
Configuration
System Bus Error Reg (R7) xCC000000C8000000
Bits in LOW LONGWORD SLICE
Follows
MADR <31:0> (R14) Has Valid Miss
Contents
6-Bit Bcache Miss Cntr:
x0000000000000024
Bits in HIGH LONGWORD SLICE
Follows
MADR <63:32> (R14) Has Valid Miss
Contents
6-Bit Bcache Miss Cntr:
x0000000000000026
System Bus Low Er Adr(R8) xE0400043E0400043
Bits in LOW LONGWORD SLICE
Follows
Address is Field <33:4>, from
CAD<31:2>
Address: x0000000038100010
Bits in HIGH LONGWORD SLICE
Follows
Address is Field <33:4>, from
CAD<63:34>
Address: x0000000038100010
System Bus Hi Er Adr (R9) x0F4000232F400023
Bits in LOW LONGWORD SLICE
Follows
Transaction Type: READ
Commander ID: CPU 1
Following Wrt Mask ONLY for AlphaServ
2100
AlphaServer 2100: Write Mask Bit 2 Set
Exchange Address: x0000000000000008
Bits in HIGH LONGWORD SLICE
Follows
Transaction Type: READ
Commander ID: CPU 1
Following Wrt Mask ONLY for AlphaServ
2100
AlphaServer 2100: NO Write Mask Bits
Set
Exchange Address: x0000000000000008
Proc Mailbox Reg (R10) x0000000000000000
Interproc Interrupt (R11) x0000000000000000
System Interrupt Clr(R12) x0000000100000000
SysBus CINT_TIM Timer Int to Local CPU
Address Lock Reg (R13) x07F2000007F20000
Bits in LOW LONGWORD SLICE
Follows
Following Lock Address Invalid (Low
Slice)
Lock Address: x0000000000FE4000
Bits in HIGH LONGWORD SLICE
Follows
Following Lock Addr Invalid (High
Slice)
Lock Address: x0000000000FE4000
Miss Address Reg (R14) x00110F6900196C11
Bits in LOW LONGWORD SLICE
Follows
Following Miss Address Valid (Low
Slice)
Commander Transaction Type: EXCHANGE
Miss Address: x0000000000065B04
Bits in HIGH LONGWORD SLICE
Follows
Following Miss Address Valid (High
Slice)
Commander Transaction Type: EXCHANGE
Miss Address: x00000000000443DA
C4 Revision Register(R15) x0002050900020509
Bits in LOW LONGWORD SLICE
Follows
C4 Bus Interface Revision: Rev C4-b
CPU Mode: DECchip 21064 Mode
Enable Read/Write Retries to I/O Space
Cache Interface Speed:
x0000000000000005
Bits in HIGH LONGWORD SLICE
Follows
C4 Bus Interface Revision: Rev C4-b
CPU Mode: DECchip 21064 Mode
Enable Read/Write Retries to I/O Space
Cache Interface Speed:
x0000000000000005
-- ENTRY FRAME FOLLOWS --
Frame ID x00000011 T2 System-Bus to PCI Bridge Frame
Byte Count x000000B8
IO Control/Status Reg xFE000002270C0180
Bit 7 Set: TLB Error Checking Enabled
Bit 8 Set: CBUS CXACK Check Enabled
Bit 18 Set: PCI Slot 1 Present
Bit 19 Set: PCI Slot 1 Present
Bit 24 Set: NOACK, CUCERR, OutOfSync
Enbld
Bit 25 Set: PCI Memory Space Enabled
Bit 26 Set: Translation Look-Aside
Enabled
Bit 29 Set: CBUS Parity Checking
Enabled
T2 Revision: Pass 2
State Machine Vis Select: CBUS Cyc
Counter
Bit 57 Set: PCI NMI Interrupts Enabled
Bit 58 Set: PCI Dev Timeout Inter
Enabled
Bit 59 Set: PCI SERR# Interrupts
Enabled
Bit 60 Set: PCI PERR# Interrupts
Enabled
Bit 61 Set: PCI Rd Data Prty Inter
Enabled
Bit 62 Set: PCI Adr Parity Inter
Enabled
Bit 63 Set: PCI Wrt Data Prty Inter
Enbled
CERR1 CBUS Error Reg 1 x0000000000000000
CERR2 Failed C/A <63:00> xE3800010E3800010
CERR3 Failed C/A <127:64> x00401FC320401FC3
PERR1 PCI Error Reg 1 x0000000000000000
PERR2 PCI Cmd & Err Addr x0000000743840E50
Failed Cmd & Addr Valid When Parity
Error
Failed PCI Cmd: x7 Memory Write
PCI Error Address: x0000000043840E50
HAE0_1 High Adr Ext Reg 1 x0000000000000010
HAE0_1 <4:0> is Sparse Mem PCI_AD
<31:27>
HAE0_2 High Adr Ext Reg 2 x0000000000000000
HBASE PC Hole Base Reg x000000000010603F
PC Hole End Addr: x000000000000003F
Bit 13 Set: PC Hole Enable 1
Bit 14 Set: PC Hole Enable 2
PC Hole Start Addr: x0000000000000020
WBASE1 Window Base Reg 1 x00000000400807FF
PCI Window End Adr: x00000000000007FF
Bit 19 Set: PCI Window Enable
PCI Window Start Adr:
x0000000000000400
WMASK1 Window Mask Reg 1 x000000003FF00000
PCI Window Mask: x00000000000003FF
TBASE1 Translated Base R1 x0000000000000000
Translated Base Addr:
x0000000000000000
WBASE2 Window Base Reg 2 x00000000000C00FF
PCI Window End Adr: x00000000000000FF
Bit 18 Set: Scatter-Gather Enable
Bit 19 Set: PCI Window Enable
PCI Window Start Adr:
x0000000000000000
WMASK2 Window Mask Reg 2 x000000000FF00000
PCI Window Mask: x00000000000000FF
TBASE2 Translated Base R2 x0000000000400000
Translated Base Addr:
x0000000000002000
TDR0 TLB Data Register 0 x00000000000006EF
TDR0 Data is Invalid
TLB Entry 0 Tag Data
x00000000000006EF
TLB Entry 0 PFN Data
x0000000000000000
TDR1 TLB Data Register 1 x0000002400000000
TDR1 Data is Invalid
TLB Entry 1 Tag Data
x0000000000000000
TLB Entry 1 PFN Data
x0000000000000012
TDR2 TLB Data Register 2 x0000000000000000
TDR2 Data is Invalid
TLB Entry 2 Tag Data
x0000000000000000
TLB Entry 2 PFN Data
x0000000000000000
TDR3 TLB Data Register 3 x0000000000000003
TDR3 Data is Invalid
TLB Entry 3 Tag Data
x0000000000000003
TLB Entry 3 PFN Data
x0000000000000000
TDR4 TLB Data Register 4 x0001BFC20010080E
TDR4 Data is Invalid
TLB Entry 4 Tag Data
x000000000010080E
TLB Entry 4 PFN Data
x000000000000DFE1
TDR5 TLB Data Register 5 x000010C40010080F
TDR5 Data is Invalid
TLB Entry 5 Tag Data
x000000000010080F
TLB Entry 5 PFN Data
x0000000000000862
TDR6 TLB Data Register 6 x0001CCC600100810
TDR6 Data is Invalid
TLB Entry 6 Tag Data
x0000000000100810
TLB Entry 6 PFN Data
x000000000000E663
TDR7 TLB Data Register 7 x000060B000100811
TDR7 Data is Invalid
TLB Entry 7 Tag Data
x0000000000100811
TLB Entry 7 PFN Data
x0000000000003058
-- ENTRY FRAME FOLLOWS --
Frame ID x00000008 Memory Frame
Byte Count x00000058
Memory Module ID x00000000
Error Register 1 x0004000100000000
[Odd] Error Summary
[Odd] EDC Corr Error
Command Trap Register 1 x00E10180E2000008
Command Trap Register 2 xF083FFFF20401CD3
Configuration Register x8009505880095058
EDC Status Register 1 x0B6A0B7B0E810D69
[Even] Read CBITS <11:0>
x0000000000000D69
[Even] Write CBITS <11:0>
x0000000000000E81
[Odd] Read CBITS <11:0>
x0000000000000B7B
[Odd] Write CBITS <11:0>
x0000000000000B6A
EDC Status Register 2 x000008BF0000000D
[Even] Syndrome <11:0>
x000000000000000D
[Odd] Syndrome <11:0>
x00000000000008BF
EDC Control Register x2000000020000000
[Even] Substitute Read Cbits Used
[Even] Substitute Write Cbits Used
[Even] Disable Inbound Parity Check
[Even] Enable EDC swap Mode
[Even] Complement Read Data Parity
[Even] Disable EDC Correction
[Even] Disable EDC Reporting
[Odd] Substitute Read Cbits Used
[Odd] Substitute Write Cbits Used
[Odd] Disable Inbound Parity Check
[Odd] Enable EDC swap Mode
[Odd] Complement Read Data Parity
[Odd] Disable EDC Correction
[Odd] Disable EDC Reporting
[Even] Subs. Read CBITS <
x0000000000000000
[Even] Subs. Write CBITS
x0000000000000000
[Odd] Subs. Read CBITS <1
x0000000000000000
[Odd] Subs. Write CBITS <
x0000000000000000
Stream Buffer Control Reg x0000080000000800
Refresh Control Register x000001D8000001D8
[Even] Refresh Enable
[Odd] Refresh Enable
[Even] Syndrome Mask <11:
x00000000000000D8
[Odd] Syndrome Mask <11:0
x00000000000000D8
Filter Control Register x0000000000000000
[Even] Syndrome Mask <11:
x0000000000000000
[Even] Bank Select x0000000000000000
[Odd] Syndrome Mask <11:0
x0000000000000000
[Odd] Bank Select x0000000000000000
-- ENTRY FRAME FOLLOWS --
Frame ID x00000008 Memory Frame
Byte Count x00000058
Memory Module ID x00000001
Error Register 1 x0000000000000000
Command Trap Register 1 xE2400008E2400008
Command Trap Register 2 x00401CD320401CD3
Configuration Register x801950A9801950A9
EDC Status Register 1 x074E0C5B04560B1B
[Even] Read CBITS <11:0>
x0000000000000B1B
[Even] Write CBITS <11:0>
x0000000000000456
[Odd] Read CBITS <11:0>
x0000000000000C5B
[Odd] Write CBITS <11:0>
x000000000000074E
EDC Status Register 2 x000000170000000D
[Even] Syndrome <11:0>
x000000000000000D
[Odd] Syndrome <11:0>
x0000000000000017
EDC Control Register x2000000020000000
[Even] Substitute Read Cbits Used
[Even] Substitute Write Cbits Used
[Even] Disable Inbound Parity Check
[Even] Enable EDC swap Mode
[Even] Complement Read Data Parity
[Even] Disable EDC Correction
[Even] Disable EDC Reporting
[Odd] Substitute Read Cbits Used
[Odd] Substitute Write Cbits Used
[Odd] Disable Inbound Parity Check
[Odd] Enable EDC swap Mode
[Odd] Complement Read Data Parity
[Odd] Disable EDC Correction
[Odd] Disable EDC Reporting
[Even] Subs. Read CBITS <
x0000000000000000
[Even] Subs. Write CBITS
x0000000000000000
[Odd] Subs. Read CBITS <1
x0000000000000000
[Odd] Subs. Write CBITS <
x0000000000000000
Stream Buffer Control Reg x0000080000000800
Refresh Control Register x000001D8000001D8
[Even] Refresh Enable
[Odd] Refresh Enable
[Even] Syndrome Mask <11:
x00000000000000D8
[Odd] Syndrome Mask <11:0
x00000000000000D8
Filter Control Register x0000000000000000
[Even] Syndrome Mask <11:
x0000000000000000
[Even] Bank Select x0000000000000000
[Odd] Syndrome Mask <11:0
x0000000000000000
[Odd] Bank Select x0000000000000000
-- ENTRY FRAME FOLLOWS --
Frame ID x00000008 Memory Frame
Byte Count x00000058
Memory Module ID x00000002
Error Register 1 x0000000000000000
Command Trap Register 1 xE2800008E2800008
Command Trap Register 2 x00401CD320401CD3
Configuration Register x802950AA802950AA
EDC Status Register 1 x0FF1091D0C210523
[Even] Read CBITS <11:0>
x0000000000000523
[Even] Write CBITS <11:0>
x0000000000000C21
[Odd] Read CBITS <11:0>
x000000000000091D
[Odd] Write CBITS <11:0>
x0000000000000FF1
EDC Status Register 2 x000000170000000D
[Even] Syndrome <11:0>
x000000000000000D
[Odd] Syndrome <11:0>
x0000000000000017
EDC Control Register x2000000020000000
[Even] Substitute Read Cbits Used
[Even] Substitute Write Cbits Used
[Even] Disable Inbound Parity Check
[Even] Enable EDC swap Mode
[Even] Complement Read Data Parity
[Even] Disable EDC Correction
[Even] Disable EDC Reporting
[Odd] Substitute Read Cbits Used
[Odd] Substitute Write Cbits Used
[Odd] Disable Inbound Parity Check
[Odd] Enable EDC swap Mode
[Odd] Complement Read Data Parity
[Odd] Disable EDC Correction
[Odd] Disable EDC Reporting
[Even] Subs. Read CBITS <
x0000000000000000
[Even] Subs. Write CBITS
x0000000000000000
[Odd] Subs. Read CBITS <1
x0000000000000000
[Odd] Subs. Write CBITS <
x0000000000000000
Stream Buffer Control Reg x0000080000000800
Refresh Control Register x000001D8000001D8
[Even] Refresh Enable
[Odd] Refresh Enable
[Even] Syndrome Mask <11:
x00000000000000D8
[Odd] Syndrome Mask <11:0
x00000000000000D8
Filter Control Register x0000000000000000
[Even] Syndrome Mask <11:
x0000000000000000
[Even] Bank Select x0000000000000000
[Odd] Syndrome Mask <11:0
x0000000000000000
[Odd] Bank Select x0000000000000000
-- ENTRY FRAME FOLLOWS --
Frame ID x00000008 Memory Frame
Byte Count x00000058
Memory Module ID x00000003
Error Register 1 x0000000000000000
Command Trap Register 1 xE2C00008E2C00008
Command Trap Register 2 x00401CD320401CD3
Configuration Register x803950AB803950AB
EDC Status Register 1 x02170AD000A50A01
[Even] Read CBITS <11:0>
x0000000000000A01
[Even] Write CBITS <11:0>
x00000000000000A5
[Odd] Read CBITS <11:0>
x0000000000000AD0
[Odd] Write CBITS <11:0>
x0000000000000217
EDC Status Register 2 x000000170000000D
[Even] Syndrome <11:0>
x000000000000000D
[Odd] Syndrome <11:0>
x0000000000000017
EDC Control Register x2000000020000000
[Even] Substitute Read Cbits Used
[Even] Substitute Write Cbits Used
[Even] Disable Inbound Parity Check
[Even] Enable EDC swap Mode
[Even] Complement Read Data Parity
[Even] Disable EDC Correction
[Even] Disable EDC Reporting
[Odd] Substitute Read Cbits Used
[Odd] Substitute Write Cbits Used
[Odd] Disable Inbound Parity Check
[Odd] Enable EDC swap Mode
[Odd] Complement Read Data Parity
[Odd] Disable EDC Correction
[Odd] Disable EDC Reporting
[Even] Subs. Read CBITS <
x0000000000000000
[Even] Subs. Write CBITS
x0000000000000000
[Odd] Subs. Read CBITS <1
x0000000000000000
[Odd] Subs. Write CBITS <
x0000000000000000
Stream Buffer Control Reg x0000080000000800
Refresh Control Register x000001D8000001D8
[Even] Refresh Enable
[Odd] Refresh Enable
[Even] Syndrome Mask <11:
x00000000000000D8
[Odd] Syndrome Mask <11:0
x00000000000000D8
Filter Control Register x0000000000000000
[Even] Syndrome Mask <11:
x0000000000000000
[Even] Bank Select x0000000000000000
[Odd] Syndrome Mask <11:0
x0000000000000000
[Odd] Bank Select x0000000000000000
-- ENTRY FRAME FOLLOWS --
Frame ID x00000000 End Frame
Byte Count x00000000
Received on Thu May 28 1998 - 21:23:04 NZST