Sorry... Dcache question with hardware stuff....
> ----------
> From: Shane Southwood
> Sent: Monday, July 16, 2001 3:13 PM
> To: 'tru64-unix-managers_at_ornl.gov'
> Subject: Sorry... Dcache question with hardware stuff....
>
> This question is hardware related, but don't tar and feather me just yet
> because it tru64 related. I've been working on a 255/233 for about 2
> weeks trying to figure out what was causing a hardware exception. It
> turns out that dia has reported a Dcache problem. I've attached the whole
> output at the end of this mail for those who want more info.
>
> My question is this.... how can you determine the amount of cache an
> alpha has from tru64? is there a tru64 equiv to Linux's /proc/cpuinfo?
> Also, is dcache the processors own internal cache? an external module?
> Any info will be appreciated. Thanks in advance.
>
> **** V3.3 ********************* ENTRY 3
> ********************************
>
>
> Logging OS 2. Digital UNIX
> System Architecture 2. Alpha
> Event sequence number 289.
> Timestamp of occurrence 13-JUL-2001 14:06:15
> Host name u1dau
>
> System type register x0000000D AlphaStation 400 or 2xx
> Number of CPUs (mpnum) x00000001
> CPU logging event (mperr) x00000000
>
> Event validity 1. O/S claims event is valid
> Event severity 1. Severe Priority
> Entry type 100. Machine Check Error - (major class)
> 2. - (minor class)
>
>
> Byte Count x02E8
> Processor Specific Offset x00000110
> System Specific Offset x000001A0
> PAL Error Type Code x00000092 D-Cache Parity Error
> PAL Frame Revision x00000001
> - ALPHA CHIP REGISTERS -
> PALTEMP1 x00000000000005B0
> PALTEMP2 x000C86F800000004
> PALTEMP3 x42F043D64334C28E
> PALTEMP4 x0000000000002000
> PALTEMP5 x0000000000000000
> PALTEMP6 xFFFFFC000037C490
> PALTEMP7 x0000000000004200
> PALTEMP8 x0000000000000400
> PALTEMP9 x0000000000000000
> PALTEMP10 xFFFFFC00003F0CF0
> PALTEMP11 x0000000000000000
> PALTEMP12 xFFFFFC00003F10B0
> PALTEMP13 xFFFFFC00003F10E0
> PALTEMP14 xFFFFFC00003F1140
> PALTEMP15 xFFFFFC00003F0E80
> PALTEMP16 xFFFFFC00003F0A00
> PALTEMP17 xFFFFFC0000709DD0
> PALTEMP18 x000000011FFFE9C0
> PALTEMP19 xFFFFFFFF8880F6D0
> PALTEMP20 xFFFFFC0000567150
> PALTEMP21 x0000000000000000
> PALTEMP22 x00505070727A7A7A
> PALTEMP23 x0000000000000000
> PALTEMP24 x0000000000000000
> PALTEMP25 x0000000000010000
> PALTEMP26 x0000002000000000
> PALTEMP27 x0000000000000000
> PALTEMP28 x0000000005098000
> PALTEMP29 xFFFFFFFC00000000
> PALTEMP30 x0000000000000001
> PALTEMP31 x0000000004B9DA38
> Exception Address Reg xFFFFFC00003EFE9A
> Exception Address Reg Provides
> Information
> About The Most Recent Exception.
> Address Points to Native-Mode
> Instruction
> If Machine Check or Math Trap
> Exception,
> PC in Exception Address is
> Correct.
> Last Exception Addr PC:
> x3FFFFF00000FBFA6
> Exception Summary Reg x0000000000000000
> Exception Mask Reg x0000000000000000
> Icache Ctrl & Status Reg x000C86F800000004
> Performance Counters Disabled
> Empty Wrt Buffer Before Issuing Next
> Inst
> Branch Prediction Selection: Not
> Taken
> JSR Stack is Disabled
> Instructions Can Only Single Issue
> If Not in PALmode, Executing Reserved
> Inst
> Opcode Will Result in OPCDEC
> Exception.
> Super Page Istream Memory Mapping
> Disabled
> Float Point Inst Will Cause FEN
> Exception
> Icache Addr Space Numb:
> x0000000000000000
> PALcode Base Address Reg x0000000000014000
> PALcode Base Address:
> x0000000000000005
> Hardware Int Enable Reg x00000000000014F0
> CRD Error Interrupts Enabled
> CPU Hrdw Interrupts Enabled Irq_h
> Pins 0,2
> CPU Hrdw Interrupts Enbld Irq_h Pins
> 3,4,5
> Performance Cntr 0 & 1 Interrupts
> Disabled
> Serial Line Interrupts Disabled
> NO AST Interrupts Enabled In Any Mode
>
> Hardware Int Request Reg x0000000000000000
> NO Hrdw Int Req With Companion Enable
> Set
> NO Softw Int Req With Companion
> Enable Set
> NO AST Int Req With Companion Enable
> Set
> Memory Management CSR x0000000000005220
> MMCSR Valid Only on Mem Mgt Err, DTB
> Miss,
> D-Stream Fault, Dcache Parity
> Error.
> Last Faulting Instruction RA Field:
> R2
> Last Faulting Instruction Opcode
> Follows:
> x29 - LDQ Load Quadword
> (Data) Cache Status Reg x0000000000000003
> This is EV45 Cache Status
> Register(C_STAT)
> EV45 Chip is Production Version of
> 21064A
> Last Load or Store Missed Dcache
> Cache Address Reg x00000007FFFFFFFF
> Abox Control Reg x000000000000942E
> Machine Checks Enabled for Uncorr
> Errors
> CRD Interrupts Enabled
> Single Entry Icache Stream Buffer
> Enabled
> Enable Super Page Dstream Virtual
> Addr Map
> VA<33:13> to PA<33:13>, if
> VA<42:41>=2.
> Lock Operation Conforms to Alpha
> Architect
> Dcache Enabled
> 16K Byte Dcache Selected
> Double Invalidate: Both EV45 Dcache
> Blocks
> Addressed By iAdr_h<12:5>
> Invalidated.
> Bus Interface Status Reg x0000000000002440
> PARITY ERROR In QW2 of Primary Cache
> Fill
> Block Hexaword During a Dcache
> Fill.
> Bus Interface Address Reg x0000000007125A40
> Address Only Valid if Bus Interface
> Status
> Register Error Bit 0,1,2, or 3 is
> Set.
> BIU Addr adr_h<33:5>:
> x00000000003892D2
> Bus Interface Control Reg x0000000810002225
> External Cache (Bcache) Enabled
> PARITY MODE: External Cache Parity
> Enabled
> Cache Rams are Output Enable
> Controlled
> Ext Cache Rd Access Time: 3 CPU
> Cycles
> Ext Cache Wrt Cycle Time: 3 CPU
> Cycles
> Size of External Cache: 256 Kbyte
> Ext Cache For Phys Addr Quad 3
> Disabled
> Ext Cache Rd Time Controlling Bcache
> Reads
> Ext Cache Wrt En Ctrl:
> x0000000000000001
> Fill Syndrome Reg x0000000000000080
> No Error in Low Long Word of Quad
> Word
> IF ECC MODE (Bus Intf Ctl Reg Bit 1
> Set),
> Upper LW of Quadword Check Bit 00
> Err.
> IF PARITY MODE(Bus Intf Ctl Reg Bit 1
> Clr)
> Upper LW of Quadword Corrupted.
> Fill Address Reg x0000000007125A40
> Addr Only Valid if Bus Interface Stat
> Reg
> ECC(Bit 8) or PARITY(Bit 10) Error
> Set.
> Cache Blk Phy Adr<33:5>
> x00000000003892D2
> Virtual Address Reg x0000000000006170
> Dstream FLT/DTB Miss VA
> x0000000000006170
> Bcache Tag Reg x0000000000406812
> Last Bcache Access Resulted in a Miss
>
> Parity Bit for Bcache Tag Status Bits
> Set
> Bcache Tag Dirty Bit Clear
> Bcache Tag Shared Bit Clear
> Bcache Tag Valid Bit Set
> Bcache Tag Addrress Parity Bit
> Asserted
> Tag Being Probed: x0000000000000340
>
> coma_gcr x000000007FB200B4
> DMA Priority
> 128 bit wide MEM
> Bcache enabled
> Bcache long writes
> coma_edsr x000000007FB2A0A0
> coma_ter x000000006FB13FF0
> sysTag<21:17> = x0000000000001FF8
> coma_elar x000000006FB133EC
> sysBus<20:5> at time of e
> x00000000000033EC
> coma_ehar x000000006FB10975
> sysBus<33:21> at time of
> x0000000000000975
> coma_ldlr x000000006FB1F937
> sysBus<20:5> last locked
> x000000000000F937
> coma_ldhr x000000006FB10000
> sysBus<31:21> last locked
> x0000000000000000
> coma_base0 x000000006FB10000
> Reg Base Adr <33:23> =
> x0000000000000000
> coma_base1 x000000006FB10000
> Reg Base Adr <33:23> =
> x0000000000000000
> coma_base2 x0000000047FF0000
> Reg Base Adr <33:23> =
> x0000000000000000
> coma_cnfg0 x0000000047FF0067
> Bank Valid
> Bank Size = 128 MB
> Column Adr Selection
> x0000000000000001
> coma_cnfg1 x0000000047FF0000
> Bank Size = 1024 MB
> Column Adr Selection
> x0000000000000000
> coma_cnfg2 x0000000047FF0000
> Bank Size = 1024 MB
> Column Adr Selection
> x0000000000000000
>
> epic_dcsr xFFFFFFFF800E001D
> Translation buffer enabled
> Prefetch enabled
> Disable correctable error
> Pass 2 Chip
> Partial Bypass
> PCI Cycle Type = IO Write
> epic_pear x0000000000804C40
> PCI error address x0000000000804C40
> epic_sear x0000000000162870
> DMA Address = x0000000000016287
> epic_tbr1 x0000000000491000
> Translation Base Adr =
> x0000000000002488
> epic_tbr2 x0000000000000000
> Translation Base Adr =
> x0000000000000000
> epic_pbr1 x00000000008C0000
> Scatter/Gather Enabled
> Window Enabled
> PCI Base Adr x0000000000000008
> epic_pbr2 x0000000040080000
> Scatter/Gather Disabled
> Window Enabled
> PCI Base Adr x0000000000000400
> epic_pmr1 x0000000000700000
> PCI Mask x0000000000000007
> epic_pmr2 x000000003FF00000
> PCI Mask x00000000000003FF
> epic_harx1 xFFFFFFFF80000000
> PCI_ad - memory space =
> x0000000000000010
> epic_harx2 x0000000000000000
> PCI_ad - memory space =
> x0000000000000000
> epic_pmlt x00000000000000FF
> Master Latency Timer = 255.
> epic_tag0 x0000000000807000
> Entry Valid
> pci_page x0000000000000101
> epic_tag1 x0000000000803000
> Entry Valid
> pci_page x0000000000000101
> epic_tag2 x0000000000805000
> Entry Valid
> pci_page x0000000000000100
> epic_tag3 x0000000000802000
> pci_page x0000000000000101
> epic_tag4 x0000000000804000
> pci_page x0000000000000100
> epic_tag5 x0000000000812000
> pci_page x0000000000000103
> epic_tag6 x0000000000814000
> pci_page x0000000000000102
> epic_tag7 x0000000000801000
> Entry Valid
> pci_page x0000000000000100
> epic_data0 x0000000000000588
> cpu_page x0000000000000162
> epic_data1 x0000000000000584
> cpu_page x0000000000000161
> epic_data2 x0000000000000586
> cpu_page x0000000000000161
> epic_data3 x0000000000000584
> cpu_page x0000000000000161
> epic_data4 x0000000000000586
> cpu_page x0000000000000161
> epic_data5 x00000000000024EA
> cpu_page x000000000000093A
> epic_data6 x0000000000001764
> cpu_page x00000000000005D9
> epic_data7 x0000000000000582
> cpu_page x0000000000000160
>
>
> **** V3.3 ********************* ENTRY 4
> ********************************
>
>
> Logging OS 2. Digital UNIX
> System Architecture 2. Alpha
> Event sequence number 290.
> Timestamp of occurrence 13-JUL-2001 14:06:17
> Host name u1dau
>
> System type register x0000000D AlphaStation 400 or 2xx
> Number of CPUs (mpnum) x00000001
> CPU logging event (mperr) x00000000
>
> Event validity 1. O/S claims event is valid
> Event severity 1. Severe Priority
> Entry type 302. ASCII Panic Message Type
> -1. - (minor class)
>
> SWI Minor class 9. ASCII Message
> SWI Minor sub class 1. Panic
>
> ASCII Message panic (cpu 0): Machine check -
> Hardware
> error
>
>
>
> **** V3.3 ********************* ENTRY 5
> ********************************
>
>
> Logging OS 2. Digital UNIX
> System Architecture 2. Alpha
> Event sequence number 0.
> Timestamp of occurrence 13-JUL-2001 14:09:47
> Host name u1dau
>
> System type register x0000000D AlphaStation 400 or 2xx
> Number of CPUs (mpnum) x00000001
> CPU logging event (mperr) x00000000
>
> Event validity 1. O/S claims event is valid
> Event severity 5. Low Priority
> Entry type 300. Start-Up ASCII Message Type
> -1. - (minor class)
>
> SWI Minor class 9. ASCII Message
> SWI Minor sub class 3. Startup
>
> ASCII Message
> Alpha boot: available memory from 0x916000 to 0x7ffe000
> Digital UNIX V4.0G (Rev. 1530); Thu Jul 5 14:50:56 EST 2001
> physical memory = 128.00 megabytes.
> available memory = 118.94 megabytes.
> using 484 buffers containing 3.78 megabytes of memory
> AlphaStation 255/233 system
> DECchip 21071
> 82378IB (SIO) PCI/ISA Bridge
> Firmware revision: 7.0
> PALcode: UNIX version 1.46
> Sysconfigtab PCI_Option entry 1 invalid.
> pci0 at nexus
> psiop0 at pci0 slot 6
> Loading SIOP: script 800200, reg 82008000, data 4058a140
> scsi0 at psiop0 slot 0
> rz0 at scsi0 target 0 lun 0 (LID=0) (WDIGTL ENTERPRISE 1.62)
> rz1 at scsi0 target 1 lun 0 (LID=1) (RICOH MP6200S 2.03)
> rz2 at scsi0 target 2 lun 0 (LID=2) (SEAGATE ST318416N 0004)
> isa0 at pci0
> gpc0 at isa0
> gpc1 not probed
> ace0 at isa0
> ace1 at isa0
> lp0 at isa0
> fdi0 at isa0
> tga0 at pci0 slot 13
> tga0: depth 8, map size 2MB, 1280x1024
> tga0: ZLXp2-E, Revision: 34
> tu0: DECchip 21040: Revision: 2.4
> tu0 at pci0 slot 14
> tu0: DEC TULIP (10Mbps) Ethernet Interface, hardware address:
> 00-00-F8-22-70-43
> tu0: console mode: selecting 10BaseT (UTP) port: half duplex
> kernel console: tga0
> dli: configured
>
>
>
> **** V3.3 ********************* ENTRY 6
> ********************************
>
>
> Logging OS 2. Digital UNIX
> System Architecture 2. Alpha
> Event sequence number 431.
> Timestamp of occurrence 16-JUL-2001 14:00:00
> Host name u1dau
>
> System type register x0000000D AlphaStation 400 or 2xx
> Number of CPUs (mpnum) x00000001
> CPU logging event (mperr) x00000000
>
> Event validity 1. O/S claims event is valid
> Event severity 5. Low Priority
> Entry type 310. Time Stamp
> -1. - (minor class)
>
>
>
Received on Mon Jul 16 2001 - 20:22:13 NZST
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