Hello Manangers,
I have to monitor the binary.errlog file from Alpha
DS20E,DU4.0f.Its Tru64 cluster using memory channel
II.
I am using Dec event 3.3, i was able to understand the
cam errors after reading the scsi drafts.But can any
one help me to understand the following error on
memeory channel? Following is the output from dia 3.3V
Even though it says that "link broken or adapter
broken" its not the case i am to ping on memory
channel.
I will summarize.
Thanks
Jayant Nashikkar
mailto:mgn321_at_yahoo.com
**** V3.3 ********************* ENTRY 246
********************************
Logging OS 2. Digital UNIX
System Architecture 2. Alpha
Event sequence number 382.
Timestamp of occurrence 25-FEB-2002
18:04:11
Host name sdp1
System type register x00000022 Systype 34.
(Regatta Family)
Number of CPUs (mpnum) x00000002
CPU logging event (mperr) x00000000
Event validity 1. O/S claims event
is valid
Event severity 3. High Priority
Entry type 104. Device Controller
Type Error
18. - (minor
class)
---- Device Profile ----
Unit 0
Product Name Memory Channel
System
Vendor DIGITAL
Subpacket Revision: x0001
PCI Frame Size: x000000A4
-- System/PCI Cfg Data -
Family ID 34.
Member ID 6.
Platform: x00220006 Regatta Family -
Goldrush
Subpacket Revision: 1. Memory Channel
Frame
Subpacket Length: x000000A4
PCI HOSE/Bus Number: 0.
PCI Device ID Number: x00000008 PCI Physical
Slot: PCI 8
Vendor/Device ID Code x00181011
Vendor: x1011 Digital Equipment
Corp.
Device: x0018 PCI Memory
Channel Adapter
Command Register x0006 I/O Space
Accesses Response: DISABLED
Memory Space
Accesses Response: Enabled
PCI Bus Master
Capability; Enabled
Monitor for
Special Cycle Ops: DISABLED
Generate Mem
Wrt/Invalidate Cmds: DISABLED
Parity Error
Detection Response: *IGNORE*
Wait Cycle
Address/Data Stepping: DISABLED
SERR# Sys Err
Driver Capability: DISABLED
Fast Back-to-Back
to Many Target: DISABLED
Status Register x0400 Device is 33 Mhz
Capable.
Device Select
Timing: Slow.
Revision ID x22 Memory Channel
Adapter 2.0
Reg Program Field x00 Level Programming
Not Implemented
Sub Class Code x80 Non-defined type
Network Controller
Base Class Code x02 Network
Controller
Cache Line Size x00 Feature not
implemented
Latency Timer Value xF8 Increments of 8
PCI clock cycles
Header Type Field x00 Single Function
Adapter
Built-In Selftest x00 No Built-In
Selftest
Window Control x08 PCI Window
Prefetch Enabled
Valid PCI Address
Space
Base Address x400000 PCITbar Field
----------- Not Recognized
Expansion Rom Base Addr x02000000
Intr Routing Code x1B
IntrPin Field x01 PCI INTA
Interrupt
Min Grant x00 No major latency
requirements
Max Grant x00 No major latency
requirements
MCLcs Reg Bits <15:00> xC07F MC Transmit Path
Error
MC Receive Path
Error
Configured as
Virtual Hub
MC Receive Error
Interrupt Enabled
MC Transmit Error
Interrupt Enabled
MC Interrupt
Enabled
Port Change
Interrupt Enabled
MC Port State
Change Interrupt
Interrupt Summary
Bit set
MCLcs Reg Bits <31:16> x0000
PCI Rec Base Addr <31:16> xE000
MCError Reg Bits <15:00> x0208 Link TX Error
Link Control
Packet Error History
MCError Reg Bits <31:16> x1202 Heartbeat Timeout
Enabled
Receive Packet
Summary Error
Link/Hub Summary
Transmit Packet Error
MCPort Reg Bits <31:16> xC200 Hub Linecard Slot
0 or VH0
Adapter Hub Type
- Virtual Hub
Port Status Timeout
7.4-8.0 sec
Link Online Disabled
Adapter Broken
Link Broken
Link Hub OK
Config Reg Bits <15:00> x000B Configuration
Jumper Override
- 8KB State
- 512MB State
- 8KB Jumper
Override
- 512MB Jumper
Override
POS Reg Bits <15:00> x0000
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Received on Fri Mar 08 2002 - 17:33:25 NZDT