DECevent V2.8 ******************************** ENTRY 1 ******************************** Logging OS 2. Digital UNIX System Architecture 2. Alpha Event sequence number 117. Timestamp of occurrence 05-JUN-2001 15:07:24 Host name alpha System type register x00000016 Alpha 4000/1200 Series Number of CPUs (mpnum) x00000003 CPU logging event (mperr) x00000000 Event validity 1. O/S claims event is valid Event severity 5. Low Priority Entry type 310. Time Stamp ** Error during CTR processing of EVT seg - Canonical buffer dump follows Entry# (record in file) 0. Canonical buff size 32736. Canonical event size 258. Canonical Event-Buffer: 15--<-12 11--<-08 07--<-04 03--<-00 :Byte Order 0000: 00000001 00000000 00000000 00000003 *................* 0010: 00000202 4E454720 33317646 534F0001 *..OSFv13 GEN....* 0020: 00000000 00000000 00000000 00000000 *................* 0030: 00750000 00000000 00000000 00000000 *..............u.* 0040: 30303432 37303531 35303630 31303032 *2001060515072400* 0050: 00000000 00000000 00000020 20202020 * ...........* 0060: 00000000 00000000 00616870 6C610000 *..alpha.........* 0070: 00000000 00000000 00000000 00000000 *................* 0080: 33317646 534F0001 00000000 00000000 *..........OSFv13* 0090: 000000FF 00000016 00000000 55504320 * CPU............* 00A0: 00000000 00000000 00000000 00000003 *................* 00B0: 00000000 00000000 00000000 00000000 *................* 00C0: 00000000 00000000 00000000 00000000 *................* 00D0: 00000000 00000000 00000000 00000000 *................* 00E0: 00000000 00000000 00000000 00000000 *................* 00F0: 00000000 00000000 00000000 00000700 *................* 0100: 00000001 * ....* ******************************** ENTRY 2 ******************************** Logging OS 2. Digital UNIX System Architecture 2. Alpha Event sequence number 4. Timestamp of occurrence 04-JUN-2001 20:17:19 Host name alpha System type register x00000016 Alpha 4000/1200 Series Number of CPUs (mpnum) x00000003 CPU logging event (mperr) x00000001 Event validity 1. O/S claims event is valid Event severity 5. Low Priority Entry type 203. LSM Note Events Type SWI Minor class 9. ASCII Message SWI Minor sub class 4. Informational ASCII Message LSM: Resynchronization of volume vol-rz8g in group rootdg finished. ******************************** ENTRY 3 ******************************** Logging OS 2. Digital UNIX System Architecture 2. Alpha Event sequence number 3. Timestamp of occurrence 04-JUN-2001 20:11:51 Host name alpha System type register x00000016 Alpha 4000/1200 Series Number of CPUs (mpnum) x00000003 CPU logging event (mperr) x00000001 Event validity 1. O/S claims event is valid Event severity 5. Low Priority Entry type 310. Time Stamp ** Error during CTR processing of EVT seg - Canonical buffer dump follows Entry# (record in file) 0. Canonical buff size 32736. Canonical event size 258. Canonical Event-Buffer: 15--<-12 11--<-08 07--<-04 03--<-00 :Byte Order 0000: 00000003 00000000 00000000 00000003 *................* 0010: 00000202 4E454720 33317646 534F0001 *..OSFv13 GEN....* 0020: 00000000 00000000 00000000 00000000 *................* 0030: 00030000 00000000 00000000 00000000 *................* 0040: 30303135 31313032 34303630 31303032 *2001060420115100* 0050: 00000000 00000000 00000020 20202020 * ...........* 0060: 00000000 00000000 00616870 6C610000 *..alpha.........* 0070: 00000000 00000000 00000000 00000000 *................* 0080: 33317646 534F0001 00000000 00000000 *..........OSFv13* 0090: 000000FF 00000016 00000000 55504320 * CPU............* 00A0: 00000000 00000000 00000001 00000003 *................* 00B0: 00000000 00000000 00000000 00000000 *................* 00C0: 00000000 00000000 00000000 00000000 *................* 00D0: 00000000 00000000 00000000 00000000 *................* 00E0: 00000000 00000000 00000000 00000000 *................* 00F0: 00000000 00000000 00000000 00000700 *................* 0100: 00000001 * ....* ******************************** ENTRY 4 ******************************** Logging OS 2. Digital UNIX System Architecture 2. Alpha Event sequence number 2. Timestamp of occurrence 04-JUN-2001 20:00:39 Host name alpha System type register x00000016 Alpha 4000/1200 Series Number of CPUs (mpnum) x00000003 CPU logging event (mperr) x00000000 Event validity 1. O/S claims event is valid Event severity 5. Low Priority Entry type 203. LSM Note Events Type SWI Minor class 9. ASCII Message SWI Minor sub class 4. Informational ASCII Message LSM: Resynchronization of volume vol-rz8g in group rootdg started. ******************************** ENTRY 5 ******************************** Logging OS 2. Digital UNIX System Architecture 2. Alpha Event sequence number 1. Timestamp of occurrence 04-JUN-2001 20:01:50 Host name alpha System type register x00000016 Alpha 4000/1200 Series Number of CPUs (mpnum) x00000001 CPU logging event (mperr) x00000000 Event validity 1. O/S claims event is valid Event severity 5. Low Priority Entry type 300. Start-Up ASCII Message Type SWI Minor class 9. ASCII Message SWI Minor sub class 3. Startup ASCII Message Alpha boot: available memory from 0x4168000 to 0xbfff2000 Digital UNIX V4.0E (Rev. 1091); Wed May 17 17:32:00 EDT 2000 physical memory = 3072.00 megabytes. available memory = 3006.55 megabytes. using 11788 buffers containing 92.09 megabytes of memory Master cpu at slot 0. Firmware revision: 5.3 PALcode: Digital UNIX version 1.21 AlphaServer 4100 5/600 8MB pci1 at mcbus0 slot 5 psiop0 at pci1 slot 1 Loading SIOP: script c0000600, reg 7f9de00, data c000a518 scsi0 at psiop0 slot 0 rz5 at scsi0 target 5 lun 0 (LID=0) (DEC RRD46 (C) DEC 0557) isp0 at pci1 slot 2 isp0: QLOGIC ISP1040B/V2 isp0: Firmware revision 5.57 (loaded by console) isp0: Fast RAM timing enabled. scsi1 at isp0 slot 0 rz8 at scsi1 target 0 lun 0 (LID=1) (DEC RZ1CF-CF (C) DEC 1614) (Wide16) rz9 at scsi1 target 1 lun 0 (LID=2) (DEC RZ1CF-CF (C) DEC 1614) (Wide16) rz10 at scsi1 target 2 lun 0 (LID=3) (DEC RZ1CF-CF (C) DEC 1614) (Wide16) rz11 at scsi1 target 3 lun 0 (LID=4) (DEC RZ1CF-CF (C) DEC 1614) (Wide16) isp1 at pci1 slot 3 isp1: QLOGIC ISP1040B/V2 - Differential Mode isp1: Firmware revision 5.57 (loaded by console) isp1: Fast RAM timing enabled. scsi16 at isp1 slot 0 rz128 at scsi16 target 0 lun 0 (LID=5) (DEC HSZ70 V71Z) (Wide16) rzb128 at scsi16 target 0 lun 1 (LID=6) (DEC HSZ70 V71Z) (Wide16) rzc128 at scsi16 target 0 lun 2 (LID=7) (DEC HSZ70 V71Z) (Wide16) rzd128 at scsi16 target 0 lun 3 (LID=8) (DEC HSZ70 V71Z) (Wide16) rze128 at scsi16 target 0 lun 4 (LID=9) (DEC HSZ70 V71Z) (Wide16) rzf128 at scsi16 target 0 lun 5 (LID=10) (DEC HSZ70 V71Z) (Wide16) rzg128 at scsi16 target 0 lun 6 (LID=11) (DEC HSZ70 V71Z) (Wide16) rzh128 at scsi16 target 0 lun 7 (LID=12) (DEC HSZ70 V71Z) (Wide16) rz129 at scsi16 target 1 lun 0 (LID=13) (DEC HSZ70 V71Z) (Wide16) rzb129 at scsi16 target 1 lun 1 (LID=14) (DEC HSZ70CCL V71Z) (Wide16) rzf129 at scsi16 target 1 lun 5 (LID=18) (DEC HSZ70 V71Z) (Wide16) rzg129 at scsi16 target 1 lun 6 (LID=19) (DEC HSZ70 V71Z) (Wide16) rzh129 at scsi16 target 1 lun 7 (LID=20) (DEC HSZ70 V71Z) (Wide16) rz130 at scsi16 target 2 lun 0 (LID=21) (DEC HSZ70 V71Z) (Wide16) rzc130 at scsi16 target 2 lun 2 (LID=23) (DEC HSZ70 V71Z) (Wide16) rze130 at scsi16 target 2 lun 4 (LID=25) (DEC HSZ70 V71Z) (Wide16) rz131 at scsi16 target 3 lun 0 (LID=29) (DEC HSZ70 V71Z) (Wide16) rzc131 at scsi16 target 3 lun 2 (LID=31) (DEC HSZ70 V71Z) (Wide16) rze131 at scsi16 target 3 lun 4 (LID=33) (DEC HSZ70 V71Z) (Wide16) rzh131 at scsi16 target 3 lun 7 (LID=36) (DEC HSZ70 V71Z) (Wide16) tu0: DECchip 21143: Revision: 3.0 tu0: auto negotiation capable device tu0 at pci1 slot 4 tu0: DEC TULIP (10/100) Ethernet Interface, hardware address: 00-00-F8-09-91-C0 tu0: auto negotiation off: selecting 100BaseTX (UTP) port: half duplex gpc0 at eisa0 pci0 at mcbus0 slot 4 eisa0 at pci0 ace0 at eisa0 ace1 at eisa0 lp0 at eisa0 fdi0 at eisa0 fd0 at fdi0 unit 0 trio0 at pci0 slot 2 trio0: S3 Trio64V+ (SVGA) Plug-N-Play, 1.0 Mb psiop1 at pci0 slot 5 Loading SIOP: script c0006600, reg 3feff00, data c0012918 scsi3 at psiop1 slot 0 tz29 at scsi3 target 5 lun 0 (LID=37) (QUANTUM DLT7000 2255) (Wide16) Created FRU table binary error log packet lvm0: configured. lvm1: configured. kernel console: trio0 dli: configured ATM Subsystem configured with 4 restart threads ATM IFMP: configured i2c: Server Management Hardware Present clubase: configured ATM UNI 3.x signalling: configured ATM IP interface: configured LAN Emulation: configured ******************************** ENTRY 6 ******************************** Logging OS 2. Digital UNIX System Architecture 2. Alpha Event sequence number 0. Timestamp of occurrence 04-JUN-2001 20:01:50 Host name alpha System type register x00000016 Alpha 4000/1200 Series Number of CPUs (mpnum) x00000001 CPU logging event (mperr) x00000000 Event validity 1. O/S claims event is valid Event severity 5. Low Priority Entry type 110. Generalized Machine State Type SWI Minor class 3. System configuration ******************** FRU Table Header ****************** FRU Table Version x00000004 Major Revision 4. Minor Revision 0. ================ System Resource Subpacket =============== Length x016F Class 1. System Resource Subpacket Type 1. System Platform Rev 2. System Variation x0000000000000865 SysType Spec: AlphaServer 4100 Rack Graphics: NO Embedded Graphics Pwr Fail Restart: Restart Primary Proc PowerFail: Full Battery Backup Console: Embedded Console MultiProcessing: MultiProcessing Support Reset Reason x00000002 Software Requested Reset Number Environ Variables 11. Manufacturer Digital Model AlphaServer 4100 Serial Number NI85113847 Revision Level A01 Console Type Revision V5.3-1, 27-OCT-1998 11:16:38 Environmental Variables auto_action:BOOT boot_dev:dkb0.0.0.2.1 dkb100.1.0.2.1 bootdef_dev:dkb0.0.0.2.1 dkb100.1.0.2.1 booted_dev: boot_file: booted_file: boot_osflags:a booted_osflags: boot_reset:ON dump_dev: enable_audit:ON --------------------- FRU Subpacket ---------------------- Length x0060 Class 2. FRU Subpacket Type 1. Standard FRU Rev 2. Alphaserver 4x00 Specific FRU Location 0. Slot Name: System Motherboard Self Test Status x00000001 Self-Test Status NOT Available Manufacturer Digital Model AlphaServer 4100 Part Number 23803-01 Serial Number KA815KL173 Revision Level A01 Firmware RevLevel * NOT Logged * Self Test Information * NOT Logged * ================ System Resource Subpacket =============== Length x0061 Class 1. System Resource Subpacket Type 2. Processor Rev 3. Processor ID 0. ID of this Processor in Multiprocessor Sys Processor Family x00000030 Alpha AXP CPU State x00000000000001CC PA, Processor Available PP, Processor Present PV, PALCODE Valid PMV, PALCODE Memory Valid PL, PALCODE Loaded HALTREQ: Default AVAILABLE PALcode PALcode Image 1 x0004001200010113 Maximum CPUs 4. PALcode Revision OpenVMS PALcode V1.19-18 PALcode Image 2 x0004001A00020115 Maximum CPUs 4. PALcode Revision UNIX PALcode V1.21-26 Processor Type x0000000200000007 EV56 (21164A), Pass 2 Processor Variation x0000000000000007 VAX-FP, VAX floating point support IEEE-FP, IEEE floating point support PE, Processor eligible to become Primary Manufacturer Digital Serial Number AY84969938 Revision Level 1 ================ System Resource Subpacket =============== Length x0026 Class 1. System Resource Subpacket Type 7. Cache Rev 2. Cache Level 4. Secondary Cache Speed (ns) 0. Cache Size (kilobytes) 8192. Cache Available 8192. Cache Write Policy x0003 Write Back Cache Err Corr Scheme x0005 Single Bit ECC Cache Type x0005 Unified Cache Status x0003 Enabled --------------------- FRU Subpacket ---------------------- Length x005A Class 2. FRU Subpacket Type 1. Standard FRU Rev 2. Alphaserver 4x00 Specific FRU Location 2. Slot Name: CPU0 Self Test Status x00000002 FRU Passed Self-Test Manufacturer Digital Model 200000007 Part Number B3006-EB Serial Number AY84969938 Revision Level 1 Firmware RevLevel V3.0 Self Test Information * NOT Logged * ================ System Resource Subpacket =============== Length x0061 Class 1. System Resource Subpacket Type 2. Processor Rev 3. Processor ID 1. Processor Family x00000030 Alpha AXP CPU State x00000000000001CC PA, Processor Available PP, Processor Present PV, PALCODE Valid PMV, PALCODE Memory Valid PL, PALCODE Loaded HALTREQ: Default AVAILABLE PALcode PALcode Image 1 x0004001200010113 Maximum CPUs 4. PALcode Revision OpenVMS PALcode V1.19-18 PALcode Image 2 x0004001A00020115 Maximum CPUs 4. PALcode Revision UNIX PALcode V1.21-26 Processor Type x0000000200000007 EV56 (21164A), Pass 2 Processor Variation x0000000000000003 VAX-FP, VAX floating point support IEEE-FP, IEEE floating point support Manufacturer Digital Serial Number AY84956224 Revision Level 1 ================ System Resource Subpacket =============== Length x0026 Class 1. System Resource Subpacket Type 7. Cache Rev 2. Cache Level 4. Secondary Cache Speed (ns) 0. Cache Size (kilobytes) 8192. Cache Available 8192. Cache Write Policy x0003 Write Back Cache Err Corr Scheme x0005 Single Bit ECC Cache Type x0005 Unified Cache Status x0003 Enabled --------------------- FRU Subpacket ---------------------- Length x005A Class 2. FRU Subpacket Type 1. Standard FRU Rev 2. Alphaserver 4x00 Specific FRU Location 3. Slot Name: CPU1 Self Test Status x00000002 FRU Passed Self-Test Manufacturer Digital Model 200000007 Part Number B3006-EB Serial Number AY84956224 Revision Level 1 Firmware RevLevel V3.0 Self Test Information * NOT Logged * ================ System Resource Subpacket =============== Length x0061 Class 1. System Resource Subpacket Type 2. Processor Rev 3. Processor ID 2. Processor Family x00000030 Alpha AXP CPU State x00000000000001CC PA, Processor Available PP, Processor Present PV, PALCODE Valid PMV, PALCODE Memory Valid PL, PALCODE Loaded HALTREQ: Default AVAILABLE PALcode PALcode Image 1 x0004001200010113 Maximum CPUs 4. PALcode Revision OpenVMS PALcode V1.19-18 PALcode Image 2 x0004001A00020115 Maximum CPUs 4. PALcode Revision UNIX PALcode V1.21-26 Processor Type x0000000200000007 EV56 (21164A), Pass 2 Processor Variation x0000000000000003 VAX-FP, VAX floating point support IEEE-FP, IEEE floating point support Manufacturer Digital Serial Number AY01500635 Revision Level 1 ================ System Resource Subpacket =============== Length x0026 Class 1. System Resource Subpacket Type 7. Cache Rev 2. Cache Level 4. Secondary Cache Speed (ns) 0. Cache Size (kilobytes) 8192. Cache Available 8192. Cache Write Policy x0003 Write Back Cache Err Corr Scheme x0005 Single Bit ECC Cache Type x0005 Unified Cache Status x0003 Enabled --------------------- FRU Subpacket ---------------------- Length x005A Class 2. FRU Subpacket Type 1. Standard FRU Rev 2. Alphaserver 4x00 Specific FRU Location 6. Slot Name: CPU2 (4100) or IOD2/3 (4000) Self Test Status x00000002 FRU Passed Self-Test Manufacturer Digital Model 200000007 Part Number B3006-EB Serial Number AY01500635 Revision Level 1 Firmware RevLevel V3.0 Self Test Information * NOT Logged * ================ System Resource Subpacket =============== Length x0061 Class 1. System Resource Subpacket Type 2. Processor Rev 3. Processor ID 3. Processor Family x00000030 Alpha AXP CPU State x00000000000001CC PA, Processor Available PP, Processor Present PV, PALCODE Valid PMV, PALCODE Memory Valid PL, PALCODE Loaded HALTREQ: Default AVAILABLE PALcode PALcode Image 1 x0004001200010113 Maximum CPUs 4. PALcode Revision OpenVMS PALcode V1.19-18 PALcode Image 2 x0004001A00020115 Maximum CPUs 4. PALcode Revision UNIX PALcode V1.21-26 Processor Type x0000000200000007 EV56 (21164A), Pass 2 Processor Variation x0000000000000003 VAX-FP, VAX floating point support IEEE-FP, IEEE floating point support Manufacturer Digital Serial Number AY01003015 Revision Level 1 ================ System Resource Subpacket =============== Length x0026 Class 1. System Resource Subpacket Type 7. Cache Rev 2. Cache Level 4. Secondary Cache Speed (ns) 0. Cache Size (kilobytes) 8192. Cache Available 8192. Cache Write Policy x0003 Write Back Cache Err Corr Scheme x0005 Single Bit ECC Cache Type x0005 Unified Cache Status x0003 Enabled --------------------- FRU Subpacket ---------------------- Length x005A Class 2. FRU Subpacket Type 1. Standard FRU Rev 2. Alphaserver 4x00 Specific FRU Location 7. Slot Name: CPU3 (4100) or IOD2/3 (4000) Self Test Status x00000002 FRU Passed Self-Test Manufacturer Digital Model 200000007 Part Number B3006-EB Serial Number AY01003015 Revision Level 1 Firmware RevLevel V3.0 Self Test Information * NOT Logged * ================ System Resource Subpacket =============== Length x001D Class 1. System Resource Subpacket Type 3. Memory Rev 2. Total Memory Size x00000C00 Mbytes Installed: 3072. Memory Available x00000C00 Mbytes Available: 3072. Interleave Mode * NOT Logged * --------------------- FRU Subpacket ---------------------- Length x0052 Class 2. FRU Subpacket Type 2. Memory FRU Rev 2. Alphaserver 4x00 Specific FRU Location 0. Slot Name: MEM0L and MEM0H Self Test Status x00000001 Self-Test Status NOT Available Total Memory Size 2048. Mega Bytes (2 Modules) Module Size 1024. Mega Bytes (per Module) Memory Base Addr x0000000000000000 Memory Module Type x0000000000000002 EDO DRAM Manufacturer Digital Model * NOT Logged * Part Number * NOT Logged * Serial Number * NOT Logged * Revision Level * NOT Logged * Firmware RevLevel * NOT Logged * Self Test Information * NOT Logged * --------------------- FRU Subpacket ---------------------- Length x0052 Class 2. FRU Subpacket Type 2. Memory FRU Rev 2. Alphaserver 4x00 Specific FRU Location 1. Slot Name: MEM1L and MEM1H Self Test Status x00000001 Self-Test Status NOT Available Total Memory Size 1024. Mega Bytes (2 Modules) Module Size 512. Mega Bytes (per Module) Memory Base Addr x0000000080000000 Memory Module Type x0000000000000002 EDO DRAM Manufacturer Digital Model * NOT Logged * Part Number * NOT Logged * Serial Number * NOT Logged * Revision Level * NOT Logged * Firmware RevLevel * NOT Logged * Self Test Information * NOT Logged * ================ System Resource Subpacket =============== Length x0048 Class 1. System Resource Subpacket Type 4. System Bus Bridge Rev 2. Bridge Level x0001 PRIMARY Sys Bus Bridge: system -> bus_type Bus Type x0002 System Bus to PCI Bus Bridge Num Registers 10. This Bus Bridge Phy Addr x000000F9E0000000 IOD# 0 Dev Type & Rev Register x06008332 CAP Chip Revision: x00000002 B3040 Module Revision: x00000003 B3050 Module Revision: x00000003 B3050 Module Type: Left Hand PCI-EISA Bus Bridge Present on PCI Segment Device Class: Host Bus to PCI Bridge MC-PCI Command Register x46460FF1 Module Self-Test Passed LED On. Delayed PCI Bus Reads Protocol: Enabled Bridge to PCI Transactions: Enabled Bridge REQUESTS 64 Bit Data Transactions Bridge ACCEPTS 64 Bit Data Transactions PCI Address Parity Check: Enabled MC Bus CMD/Addr Parity Check: Enabled MC Bus NXM Check: Enabled Check ALL Transactions for Errors Use MC_BMSK for 16 Byte Align Blk Mem Wrt Wrt PEND_NUM Threshold: 6. RD_TYPE Memory Prefetch Algorithm: Short RL_TYPE Mem Rd Line Prefetch Type: Medium RM_TYPE Mem Rd Multiple Cmd Type: Long ARB_MODE PCI Arbitration: Round Robin Mem Host Address Ext Reg x00000000 HAE Sparse Mem Adr<31:27> x00000000 IO Host Adr Ext Register x00000000 PCI Upper Adr Bits<31:25> x00000000 Interrupt Ctrl Register x00000003 Write Device Interrupt Info Struct:Enabled Intr Target Dev Register x0000003A Intr Trgt-0 Dev ID(Octal) o72 Intr Trgt-1 Dev ID(Octal) o0 Intr Target Addr Register x00006000 Int Trgt Data Struct Ofst x00000000 Int Info Mem Trgt Pg Addr x00000006 Int Trgt Adr Ext Register x00000000 Int Info Mem Upr Adr Bits x00000000 Interrupt Mask0 Register x00250000 Interrupt Mask1 Register x00000000 ================ System Resource Subpacket =============== Length x00F8 Class 1. System Resource Subpacket Type 6. EISA Rev 2. - ESC Registers - 26. Revision ID x13 Unrecognized Mode Select Register x24 PIRQx# Mux/Map Ctrl<2:0>: x04 NMI on SERR(SysErr) Sig Disabled GPCS[2:0]# Functions Selected Config RAM Page Adr Gen Enabled MREQ[7:4]#/PIRQ[3:0]# Disabled BIOS Chip Select A x1F Low BIOS 1 Enabled Low BIOS 2 Enabled Low BIOS 3 Enabled Low BIOS 4 Enabled High BIOS Enabled BIOS Chip Select B x00 EISA Clock Divisor xC0 Clock Divisor = 4 (33.33MHz) Peripheral Chip Sel A x83 Real Time Clock Decode Enabled Keyboard Controller Decode Enabled Floppy/IDE Decode: 0b00 Primary Flpy Addr Rang Enabled Keyboard Ctlr Mapped to X-Bus Peripheral Chip Sel B xC4 Serial Port A Adr Decode: 0b00 Serial Port B Adr Decode: 0b01 LPT1 Port Decode Enabled PORT 92 Decode Enabled CRAM Decode Enabled EISA ID Byte 1 x10 EISA ID Byte 2 xA3 EISA ID Byte 3 x64 EISA ID Byte 4 x00 Scatter/Gather Base Addr x00 PIRQ Route CSR-0 x00 IRQ Routing Bits <06:00>: Reserved IRQx Routing of Interrupts Enabled PIRQ Route CSR-1 x00 IRQ Routing Bits <06:00>: Reserved IRQx Routing of Interrupts Enabled PIRQ Route CSR-2 x00 IRQ Routing Bits <06:00>: Reserved IRQx Routing of Interrupts Enabled PIRQ Route CSR-3 x00 IRQ Routing Bits <06:00>: Reserved IRQx Routing of Interrupts Enabled Gen Purp Chip Sel Addr 0 x0530 Gen Purp Chip Sel Mask 0 x01 Gen Purp Chip Sel Addr 1 x0026 Gen Purp Chip Sel Mask 1 x01 Gen Purp Chip Sel Addr 2 x0500 Gen Purp Chip Sel Mask 2 x1F Gen Purp Chip X-Bus Ctrl xFB GPCS 0 XBUSOE# Generates Enabled GPCS 1 XBUSOE# Generates Enabled -- PCEB Registers -- 17. Vendor/Device ID Code x04828086 Vendor: x8086 Intel Device: x0482 Intel 82375EB ** PCI-to-EISA BRIDGE ** PCI Command Low <7:0> x00000007 I/O Space Enabled Memory Space Enabled Bus Master Enabled Special Cycle Not Supported Mem Write Invalidate Not Supported VGA Palette Snoop Not Supported Parity Checking Disabled Wait State Control Not Supported PCI Command High <15:8> x00000000 SERR# Disabled Revision ID x00000015 Master Latency Timer x000000F8 Count: 31. PCI Control x00000060 Slow Sample Point Interrupt Acknowledge Enabled EISA-to-PCI Line Buf Enabled PCI Arbiter Control x0000009D Guaranteed Access Time Mod Enabled Bus Lock Disbled Bus Park Enabled Retries unmasked after 64 PCICLK's Auto-PEREQ# Control Enabled PCI Arbiter Priority Ctrl x000000F0 B0PRI = PCEBREQ# > REQ0# B1PRI = CPUREQ# > REQ3# B2PRI = Bank0 > Bank3 > Bank1 Bank 0 Rotate Control Enabled Bank 1 Rotate Control Enabled Bank 2 Rotate Control Enabled Bank 3 Rotate Control Enabled PCI Decode Control x00000020 Subtractive Decode (82375SB Only) IDEDC Positive Decode Disabled 8259C Positive Decode Enabled EISA-to-PCI Mem Attribute x00000001 Region 1 Buffered Access Region 2 Non-Buffered Access Region 3 Non-Buffered Access Region 4 Non-Buffered Access Mem Region 1 Addr <7:0> x00000000 Mem Region 1 Addr <15:8> x00000000 Mem Region 1 Addr <23:16> x000000FF Mem Region 1 Addr <31:24> x000000FF Number of EISA Devices - 4. ** Platform/Configuration Specific EISA SLOT Identification Slot 1. ** Device NOT Present Slot 2. ** Device NOT Present Slot 3. ** Device NOT Present Slot 4. ** Device NOT Present ================ System Resource Subpacket =============== Length x0058 Class 1. System Resource Subpacket Type 5. PCI Rev 1. PCI Device Registers ---- PCI Configuration Addr x000000F9C0010018 PCI: 0 Bus: 0 Device Number: 1 Vendor/Device ID Code x04828086 Vendor: x8086 Intel Device: x0482 Intel 82375EB ** PCI-to-EISA BRIDGE ** Command Register x0007 I/O Space Accesses Response: Enabled Memory Space Accesses Response: Enabled PCI Bus Master Capability; Enabled Monitor for Special Cycle Ops: DISABLED Generate Mem Wrt/Invalidate Cmds: DISABLED Parity Error Detection Response: *IGNORE* Wait Cycle Address/Data Stepping: DISABLED SERR# Sys Err Driver Capability: DISABLED Fast Back-to-Back to Many Target: DISABLED Status Register x0200 Device is 33 Mhz Capable. No Support for User Defineable Features. Fast Back-to-Back to Different Targets, Is Not Supported in Target Device. Device Select Timing: Medium. Device Revision x15 Device Class Code x000000 Zero's: Undefined or No Class Code Support Sys Cache Line Size x00 Latency Timer Value xF8 Header Type x00 Single Function Device Built-in Self Test CSR x00 Base Address Register 1 x00000000 Base Address Register 2 x00000000 Base Address Register 3 x00000000 Base Address Register 4 x00000000 Base Address Register 5 x00000000 Base Address Register 6 x00000000 Expansion Rom Base Addr x00000000 Interrupt Line Routing x00 Interrupt Pin Being Used x00 Min Bus Grant/Burst x00 Max Bus Latency x00 ================ System Resource Subpacket =============== Length x0058 Class 1. System Resource Subpacket Type 5. PCI Rev 1. PCI Device Registers ---- PCI Configuration Addr x000000F9C0020018 PCI: 0 Bus: 0 Device Number: 2 Vendor/Device ID Code x88115333 Vendor: x5333 S3 VISION INC. Device: x8811 Chip: 86C764 - S3 Vision Trio64/Trio32 v1 Command Register x0003 I/O Space Accesses Response: Enabled Memory Space Accesses Response: Enabled PCI Bus Master Capability; DISABLED Monitor for Special Cycle Ops: DISABLED Generate Mem Wrt/Invalidate Cmds: DISABLED Parity Error Detection Response: *IGNORE* Wait Cycle Address/Data Stepping: DISABLED SERR# Sys Err Driver Capability: DISABLED Fast Back-to-Back to Many Target: DISABLED Status Register x0200 Device is 33 Mhz Capable. No Support for User Defineable Features. Fast Back-to-Back to Different Targets, Is Not Supported in Target Device. Device Select Timing: Medium. Device Revision x54 Device Class Code x030000 Display Controller: VGA Compatible Ctlr Sys Cache Line Size x00 Latency Timer Value x00 Header Type x00 Single Function Device Built-in Self Test CSR x00 Base Address Register 1 x04000000 Base Address Register 2 x00000000 Base Address Register 3 x00000000 Base Address Register 4 x00000000 Base Address Register 5 x00000000 Base Address Register 6 x00000000 Expansion Rom Base Addr x03FF0000 Interrupt Line Routing x08 Interrupt Pin Being Used x01 Min Bus Grant/Burst x00 Max Bus Latency x00 ================ System Resource Subpacket =============== Length x0058 Class 1. System Resource Subpacket Type 5. PCI Rev 1. PCI Device Registers ---- PCI Configuration Addr x000000F9C0050018 PCI: 0 Bus: 0 Device Number: 5 Vendor/Device ID Code x00011000 Vendor: x1000 NCR Device: x0001 NCR 53C810 Fast/Narrow SCSI Controller Command Register x0147 I/O Space Accesses Response: Enabled Memory Space Accesses Response: Enabled PCI Bus Master Capability; Enabled Monitor for Special Cycle Ops: DISABLED Generate Mem Wrt/Invalidate Cmds: DISABLED Parity Error Detection Response: Normal Wait Cycle Address/Data Stepping: DISABLED SERR# Sys Err Driver Capability: Enabled Fast Back-to-Back to Many Target: DISABLED Status Register x0200 Device is 33 Mhz Capable. No Support for User Defineable Features. Fast Back-to-Back to Different Targets, Is Not Supported in Target Device. Device Select Timing: Medium. Device Revision x02 Device Class Code x010000 Mass Storage: SCSI Bus Controller Sys Cache Line Size x00 Latency Timer Value xFF Header Type x00 Single Function Device Built-in Self Test CSR x00 Base Address Register 1 x01FFFF01 Base Address Register 2 x03FEFF00 Base Address Register 3 x00000000 Base Address Register 4 x00000000 Base Address Register 5 x00000000 Base Address Register 6 x00000000 Expansion Rom Base Addr x00000000 Interrupt Line Routing x14 Interrupt Pin Being Used x01 Min Bus Grant/Burst x00 Max Bus Latency x00 ================ System Resource Subpacket =============== Length x0048 Class 1. System Resource Subpacket Type 4. System Bus Bridge Rev 2. Bridge Level x0001 PRIMARY Sys Bus Bridge: system -> bus_type Bus Type x0002 System Bus to PCI Bus Bridge Num Registers 10. This Bus Bridge Phy Addr x000000FBE0000000 IOD# 1 Dev Type & Rev Register x06000332 CAP Chip Revision: x00000002 B3040 Module Revision: x00000003 B3050 Module Revision: x00000003 B3050 Module Type: Left Hand Internal CAP Chip Arbiter: Enabled Device Class: Host Bus to PCI Bridge MC-PCI Command Register x46460FF1 Module Self-Test Passed LED On. Delayed PCI Bus Reads Protocol: Enabled Bridge to PCI Transactions: Enabled Bridge REQUESTS 64 Bit Data Transactions Bridge ACCEPTS 64 Bit Data Transactions PCI Address Parity Check: Enabled MC Bus CMD/Addr Parity Check: Enabled MC Bus NXM Check: Enabled Check ALL Transactions for Errors Use MC_BMSK for 16 Byte Align Blk Mem Wrt Wrt PEND_NUM Threshold: 6. RD_TYPE Memory Prefetch Algorithm: Short RL_TYPE Mem Rd Line Prefetch Type: Medium RM_TYPE Mem Rd Multiple Cmd Type: Long ARB_MODE PCI Arbitration: Round Robin Mem Host Address Ext Reg x00000000 HAE Sparse Mem Adr<31:27> x00000000 IO Host Adr Ext Register x00000000 PCI Upper Adr Bits<31:25> x00000000 Interrupt Ctrl Register x00000003 Write Device Interrupt Info Struct:Enabled Intr Target Dev Register x0000003A Intr Trgt-0 Dev ID(Octal) o72 Intr Trgt-1 Dev ID(Octal) o0 Intr Target Addr Register x00006004 Int Trgt Data Struct Ofst x00000001 Int Info Mem Trgt Pg Addr x00000006 Int Trgt Adr Ext Register x00000000 Int Info Mem Upr Adr Bits x00000000 Interrupt Mask0 Register x00000000 Interrupt Mask1 Register x00000000 ================ System Resource Subpacket =============== Length x0058 Class 1. System Resource Subpacket Type 5. PCI Rev 1. PCI Device Registers ---- PCI Configuration Addr x000000FBC0010018 PCI: 1 Bus: 0 Device Number: 1 Vendor/Device ID Code x00011000 Vendor: x1000 NCR Device: x0001 NCR 53C810 Fast/Narrow SCSI Controller Command Register x0147 I/O Space Accesses Response: Enabled Memory Space Accesses Response: Enabled PCI Bus Master Capability; Enabled Monitor for Special Cycle Ops: DISABLED Generate Mem Wrt/Invalidate Cmds: DISABLED Parity Error Detection Response: Normal Wait Cycle Address/Data Stepping: DISABLED SERR# Sys Err Driver Capability: Enabled Fast Back-to-Back to Many Target: DISABLED Status Register x0200 Device is 33 Mhz Capable. No Support for User Defineable Features. Fast Back-to-Back to Different Targets, Is Not Supported in Target Device. Device Select Timing: Medium. Device Revision x02 Device Class Code x010000 Mass Storage: SCSI Bus Controller Sys Cache Line Size x00 Latency Timer Value xFF Header Type x00 Single Function Device Built-in Self Test CSR x00 Base Address Register 1 x01FFFC01 Base Address Register 2 x07F9DE00 Base Address Register 3 x00000000 Base Address Register 4 x00000000 Base Address Register 5 x00000000 Base Address Register 6 x00000000 Expansion Rom Base Addr x00000000 Interrupt Line Routing x04 Interrupt Pin Being Used x01 Min Bus Grant/Burst x00 Max Bus Latency x00 ================ System Resource Subpacket =============== Length x0058 Class 1. System Resource Subpacket Type 5. PCI Rev 1. PCI Device Registers ---- PCI Configuration Addr x000000FBC0020018 PCI: 1 Bus: 0 Device Number: 2 Vendor/Device ID Code x10201077 Vendor: x1077 QLogic Device: x1020 QLogic ISP_1020A/1040A SCSI Ctrl Command Register x0147 I/O Space Accesses Response: Enabled Memory Space Accesses Response: Enabled PCI Bus Master Capability; Enabled Monitor for Special Cycle Ops: DISABLED Generate Mem Wrt/Invalidate Cmds: DISABLED Parity Error Detection Response: Normal Wait Cycle Address/Data Stepping: DISABLED SERR# Sys Err Driver Capability: Enabled Fast Back-to-Back to Many Target: DISABLED Status Register x0200 Device is 33 Mhz Capable. No Support for User Defineable Features. Fast Back-to-Back to Different Targets, Is Not Supported in Target Device. Device Select Timing: Medium. Device Revision x05 Device Class Code x010000 Mass Storage: SCSI Bus Controller Sys Cache Line Size x10 Latency Timer Value xF8 Header Type x00 Single Function Device Built-in Self Test CSR x00 Base Address Register 1 x01FFFD01 Base Address Register 2 x07F9E000 Base Address Register 3 x00000000 Base Address Register 4 x00000000 Base Address Register 5 x00000000 Base Address Register 6 x00000000 Expansion Rom Base Addr x07FA0000 Interrupt Line Routing x08 Interrupt Pin Being Used x01 Min Bus Grant/Burst x00 Max Bus Latency x00 ================ System Resource Subpacket =============== Length x0058 Class 1. System Resource Subpacket Type 5. PCI Rev 1. PCI Device Registers ---- PCI Configuration Addr x000000FBC0030018 PCI: 1 Bus: 0 Device Number: 3 Vendor/Device ID Code x10201077 Vendor: x1077 QLogic Device: x1020 QLogic ISP_1020A/1040A SCSI Ctrl Command Register x0147 I/O Space Accesses Response: Enabled Memory Space Accesses Response: Enabled PCI Bus Master Capability; Enabled Monitor for Special Cycle Ops: DISABLED Generate Mem Wrt/Invalidate Cmds: DISABLED Parity Error Detection Response: Normal Wait Cycle Address/Data Stepping: DISABLED SERR# Sys Err Driver Capability: Enabled Fast Back-to-Back to Many Target: DISABLED Status Register x0200 Device is 33 Mhz Capable. No Support for User Defineable Features. Fast Back-to-Back to Different Targets, Is Not Supported in Target Device. Device Select Timing: Medium. Device Revision x05 Device Class Code x010000 Mass Storage: SCSI Bus Controller Sys Cache Line Size x10 Latency Timer Value xF8 Header Type x00 Single Function Device Built-in Self Test CSR x00 Base Address Register 1 x01FFFE01 Base Address Register 2 x07F9F000 Base Address Register 3 x00000000 Base Address Register 4 x00000000 Base Address Register 5 x00000000 Base Address Register 6 x00000000 Expansion Rom Base Addr x07FB0000 Interrupt Line Routing x0C Interrupt Pin Being Used x01 Min Bus Grant/Burst x00 Max Bus Latency x00 ================ System Resource Subpacket =============== Length x0058 Class 1. System Resource Subpacket Type 5. PCI Rev 1. PCI Device Registers ---- PCI Configuration Addr x000000FBC0040018 PCI: 1 Bus: 0 Device Number: 4 Vendor/Device ID Code x00191011 Vendor: x1011 Digital Equipment Corp. Device: x0019 DC21143 TWINNET PCI/CardBus 10/100 Mbit, Dual Ethernet Controller Command Register x0147 I/O Space Accesses Response: Enabled Memory Space Accesses Response: Enabled PCI Bus Master Capability; Enabled Monitor for Special Cycle Ops: DISABLED Generate Mem Wrt/Invalidate Cmds: DISABLED Parity Error Detection Response: Normal Wait Cycle Address/Data Stepping: DISABLED SERR# Sys Err Driver Capability: Enabled Fast Back-to-Back to Many Target: DISABLED Status Register x0280 Device is 33 Mhz Capable. No Support for User Defineable Features. Fast Back-to-Back to Different Targets, Is Supported in Target Device. Device Select Timing: Medium. Device Revision x30 Device Class Code x020000 Network Controller: Ethernet Controller Sys Cache Line Size x10 Latency Timer Value xFF Header Type x00 Single Function Device Built-in Self Test CSR x00 Base Address Register 1 x01FFFF01 Base Address Register 2 x07F9DF00 Base Address Register 3 x00000000 Base Address Register 4 x00000000 Base Address Register 5 x00000000 Base Address Register 6 x00000000 Expansion Rom Base Addr x07FC0000 Interrupt Line Routing x10 Interrupt Pin Being Used x01 Min Bus Grant/Burst x14 Max Bus Latency x28 --------------------- FRU Subpacket ---------------------- Length x004F Class 2. FRU Subpacket Type 1. Standard FRU Rev 2. Alphaserver 4x00 Specific FRU Location 5. Slot Name: IOD0/1 Self Test Status x00000002 FRU Passed Self-Test Manufacturer Digital Model 0 Part Number B3040-AA Serial Number KA729YMJBB Revision Level 32 Firmware RevLevel * NOT Logged * Self Test Information * NOT Logged * --------------------- FRU Subpacket ---------------------- Length x0052 Class 2. FRU Subpacket Type 1. Standard FRU Rev 2. Alphaserver 4x00 Specific FRU Location 10. B3050 Module (Left Hand) Self Test Status x00000002 FRU Passed Self-Test Manufacturer Digital Model 0 Part Number B3052-AA Serial Number KA818NW727 Revision Level 3 Firmware RevLevel V5.3 Self Test Information * NOT Logged * ================ System Resource Subpacket =============== Length x0028 Class 1. System Resource Subpacket Type 8. Power Rev 2. Number of Elements 2. Element Type x0001 DC Power Supply ID No 0. Status x00000001 OK Element Type x0001 DC Power Supply ID No 2. Status x00000001 OK ================ System Resource Subpacket =============== Length x0F04 Class 1. System Resource Subpacket Type 10. System Initialization Log Rev 1. System Init Log 23:35.14 initializing overlays 23:35.14 XDELTA not enabled. 23:35.14 initializing flash index 23:35.14 hf_init 23:35.14 flash index count = 68, adr = cec14 23:35.14 flash seq_minor = 10003, var_major = 560005 23:35.14 starting console on CPU 0 23:35.14 initializing file system 23:35.14 DDB Startup, phase = 0 23:35.14 DDB Startup nl 23:35.14 DDB Startup rd 23:35.14 DDB Startup buf 23:35.14 DDB Startup flash 23:35.14 DDB Startup sym 23:35.14 initializing timer data structures 23:35.14 lowering IPL 23:35.15 CPU 0 speed is 1.67 ns (599MHz) 23:35.15 DDB Startup, phase = 1 23:35.15 DDB Startup tt 23:35.15 DDB Startup combo 23:35.15 DDB Startup pmem 23:35.15 DDB Startup examine 23:35.15 DDB Startup esc_nvram 23:35.15 DDB Startup nvram 23:35.15 access NVRAM 23:35.15 DDB Startup iic 23:35.15 DDB Startup sable_ocp 23:35.15 DDB Startup toy 23:35.15 slot 7 - CPU 23:35.15 slot 6 - CPU 23:35.15 slot 5 IOD (6000) - hose 1 23:35.15 slot 4 IOD (6008) - hose 0 23:35.15 slot 3 - CPU 23:35.15 slot 2 - CPU 23:35.15 slot 1 - MEM 23:35.15 Loading startup overlays 23:35.15 DDB Startup, phase = 2 23:35.15 DDB Startup ev 23:35.15 entering idle loop 23:35.15 Loading start2 overlays 23:35.16 DDB Startup, phase = 3 23:35.16 DDB Startup el 23:35.16 DDB Startup vmem 23:35.16 DDB Startup ev5_ipr 23:35.16 DDB Startup gpr 23:35.16 DDB Startup fpr 23:35.16 DDB Startup pt 23:35.16 DDB Startup ps 23:35.16 DDB Startup pi 23:35.16 DDB Startup tee 23:35.16 DDB Startup decode 23:35.16 memzone: base = 1000000, mz_size = 7f000000 23:35.16 halt code = 34 23:35.16 PC = 1d8 23:35.16 starting console on CPU 1 23:35.16 lowering IPL 23:35.16 halt code = 34 23:35.16 PC = 1d8 23:35.16 starting console on CPU 2 23:35.16 lowering IPL 23:35.16 halt code = 34 23:35.16 PC = 1d8 23:35.16 starting console on CPU 3 23:35.16 lowering IPL 23:35.16 CPU 1 speed is 1.67 ns (599MHz) 23:35.16 entering idle loop 23:35.16 CPU 2 speed is 1.67 ns (599MHz) 23:35.16 CPU 3 speed is 1.67 ns (599MHz) 23:35.16 entering idle loop 23:35.16 entering idle loop 23:35.24 Executing iod_diag on device iod0 23:35.25 iod0 passed power-up tests 23:35.25 Executing iod_diag on device iod1 23:35.25 iod1 passed power-up tests 23:35.25 Executing pceb_diag 23:35.26 pceb passed power-up tests 23:35.26 Executing esc_diag 23:35.26 esc passed power-up tests 23:35.26 Executing ds1287_diag 23:35.26 toy passed power-up tests 23:35.26 Executing combo_diag 23:35.27 combo passed power-up tests 23:35.27 Executing ncr810_diag 23:35.27 n810 passed power-up tests 23:35.27 Initializing VGA 23:35.27 Starting Bios Emulator 23:35.27 Loading X86 & X86A 23:35.32 Created x86_process: pid 15 23:35.34 Completed Bios Emulation, status = 0 23:35.34 KBD h/s/b/f/c/dev/vect 0/0/1/1/0/11fb80/81 23:35.34 MOUSE h/s/b/f/c/dev/vect 0/0/1/2/0/11fca0/8c 23:35.34 initializing keyboard 23:35.36 kbd test passed 23:35.36 mouse test passed 23:35.36 Initialize VGA hardware 23:35.36 Stopping X86 Bios 23:35.36 Completed VGA 23:35.36 resetting the SCSI bus on pka0.7.0.1.1 23:35.37 port pka0.7.0.1.1 initialized, scripts are at 1287e0 23:35.38 resetting the SCSI bus on pkb0.7.0.2.1 23:35.38 clearing interrupt vector 000000b8 23:35.38 free all semaphores 23:35.38 free all dynamic memory 23:35.39 resetting the SCSI bus on pkc0.7.0.3.1 23:35.39 clearing interrupt vector 000000bc 23:35.39 free all semaphores 23:35.39 free all dynamic memory 23:35.40 resetting the SCSI bus on pkd0.7.0.5.0 23:35.41 port pkd0.7.0.5.0 initialized, scripts are at 12adc0 23:35.42 Created device: dkb0.0.0.2.1 23:35.43 resetting the SCSI bus on pkb0.7.0.2.1 23:35.44 sense key = 'Unit Attention' (29|02) from dkb0.0.0.2.1 23:35.45 breaking virtual connection with sb 00126700 23:35.45 clearing interrupt vector 000000b8 23:35.45 free all semaphores 23:35.45 free all dynamic memory ******************************** ENTRY 7 ******************************** Logging OS 2. Digital UNIX System Architecture 2. Alpha Event sequence number 4. Timestamp of occurrence 04-JUN-2001 19:58:17 Host name alpha System type register x00000016 Alpha 4000/1200 Series Number of CPUs (mpnum) x00000003 CPU logging event (mperr) x00000000 Event validity 1. O/S claims event is valid Event severity 1. Severe Priority Entry type 302. ASCII Panic Message Type SWI Minor class 9. ASCII Message SWI Minor sub class 1. Panic ASCII Message panic (cpu 0): System Uncorrectable Machine Check ******************************** ENTRY 8 ******************************** Logging OS 2. Digital UNIX System Architecture 2. Alpha Event sequence number 3. Timestamp of occurrence 04-JUN-2001 19:58:16 Host name alpha System type register x00000016 Alpha 4000/1200 Series Number of CPUs (mpnum) x00000003 CPU logging event (mperr) x00000000 Event validity 1. O/S claims event is valid Event severity 1. Severe Priority Entry type 100. CPU Machine Check Errors CPU Minor class 2. 660 Entry Software Flags x0000000300000000 IOD 0 Register Subpkt Pres IOD 1 Register Subpkt Pres Active CPUs x00000007 Hardware Rev x00000000 System Serial Number NI85113847 Module Serial Number Module Type x0000 System Revision x00000000 * MCHK 660 Regs * Flags: x00000000 PCI Mask x0000 Machine Check Reason x0202 IOD-Detected Hard Error -OR- DTag Parity Error (If Cached CPU) PAL SHADOW REG 0 x0000000000000000 PAL SHADOW REG 1 x0000000000000000 PAL SHADOW REG 2 x0000000000000000 PAL SHADOW REG 3 x0000000000000000 PAL SHADOW REG 4 x0000000000000000 PAL SHADOW REG 5 x0000000000000000 PAL SHADOW REG 6 x0000000000000000 PAL SHADOW REG 7 x0000000000000000 PALTEMP0 x0000000000000000 PALTEMP1 x0000000000000000 PALTEMP2 xFFFFFC0000531010 PALTEMP3 x0000000000004400 PALTEMP4 x0000000000000000 PALTEMP5 xFFFFFC0000720A50 PALTEMP6 x0000000000000000 PALTEMP7 xFFFFFC0000530930 PALTEMP8 x1F1E171515020100 PALTEMP9 xFFFFFC0000530D50 PALTEMP10 xFFFFFC00002BB294 PALTEMP11 xFFFFFC0000530BB0 PALTEMP12 xFFFFFC0000530F80 PALTEMP13 x0000000000006E80 PALTEMP14 x0000000000000000 PALTEMP15 x00000000000F0000 PALTEMP16 x0000020306600001 PALTEMP17 x0000000000000000 PALTEMP18 x0000000000000000 PALTEMP19 xFFFFFFFE9C2B3A38 PALTEMP20 x0000000001050000 PALTEMP21 xFFFFFC0000530FB0 PALTEMP22 xFFFFFC0000720A50 PALTEMP23 x00000000B9C05A38 Exception Address Reg xFFFFFC00002BB294 Native-mode Instruction Exception PC x3FFFFF00000AECA5 Exception Summary Reg x0000000000000000 Exception Mask Reg x0000000000000000 PAL Base Address Reg x0000000000014000 Base Addr for PALcode: x0000000000000005 Interrupt Summary Reg x0000000000200000 External HW Interrupt at IPL21 AST Requests 3-0: x0000000000000000 IBOX Ctrl and Status Reg x000000C160020000 Timeout Counter Bit Clear. IBOX Timeout Counter Enabled. Floating Point Instructions will Cause FEN Exceptions. PAL Shadow Registers Enabled. Correctable Error Interrupts Enabled. ICACHE BIST (Self Test) Was Successful. TEST_STATUS_H Pin Asserted Icache Par Err Stat Reg x0000000000000000 Dcache Par Err Stat Reg x0000000000000000 Virtual Address Reg x0000000140002A38 Memory Mgmt Flt Sts Reg x0000000000014850 If Err, Reference Resulted in DTB Miss Fault Inst RA Field: x0000000000000001 Fault Inst Opcode: x0000000000000029 Scache Address Reg xFFFFFF000001900F Scache Status Reg x0000000000000000 Bcache Tag Address Reg xFFFFFF809B8EEFFF Last Bcache Access Resulted in a Miss. Value of Parity Bit for Tag Control Status Bits Dirty, Shared & Valid is Set. Value of Tag Control Dirty Bit is Set. Value of Tag Control Shared Bit is Set. Value of Tag Control Valid Bit is Clear. Value of Parity Bit Covering Tag Store Address Bits is Set. Tag Address<38:20> Is: x00000000000009B8 Ext Interface Address Reg xFFFFFF00A21842DF Fill Syndrome Reg x00000000000000DD Ext Interface Status Reg xFFFFFFF005FFFFFF Error Occurred During D-ref Fill LD LOCK xFFFFFF0097A8718F ** IOD SUBPACKET -> ** IOD 0 Register Subpacket WHOAMI x0000033A Module Revision 0. VCTY ASIC Rev = 1 CPU = 0 This Bus Bridge Phy Addr x000000F9E0000000 IOD# 0 Dev Type & Rev Register x06008332 CAP Chip Revision: x00000002 B3040 Revision: x00000003 B3050 Revision: x00000003 AlphaServer 4100 MC-PCI Command Register x46460FF1 Module Self-Test Passed LED On. Delayed PCI Bus Reads Protocol: Enabled Bridge to PCI Transactions: Enabled Bridge REQUESTS 64 Bit Data Transactions Bridge ACCEPTS 64 Bit Data Transactions PCI Address Parity Check: Enabled MC Bus CMD/Addr Parity Check: Enabled MC Bus NXM Check: Enabled Check ALL Transactions for Errors Use MC_BMSK for 16 Byte Align Blk Mem Wrt Wrt PEND_NUM Threshold: 6. RD_TYPE Memory Prefetch Algorithm: Short RL_TYPE Mem Rd Line Prefetch Type: Medium RM_TYPE Mem Rd Multiple Cmd Type: Long ARB_MODE PCI Arbitration: Round Robin Mem Host Address Ext Reg x00000000 HAE Sparse Mem Adr<31:27> x00000000 IO Host Adr Ext Register x00000000 PCI Upper Adr Bits<31:25> x00000000 Interrupt Ctrl Register x00000003 Write Device Interrupt Info Struct:Enabled Interrupt Request x00800000 Interrupts asserted x00000000 Hard Error Interrupt Mask0 Register x00C51000 Interrupt Mask1 Register x00000000 MC Error Info Register 0 x148840E0 MC Bus Trans Addr<31:4>: 148840E0 MC Error Info Register 1 x800EDB00 MC bus trans addr <39:32> x00000000 MC Command is ReadMod1-Mem CPU1 Master at Time of Error Device ID: x00000003 MC error info valid CAP Error Register xA0000000 Uncorrectable ECC err det by MDPA MC error info latched PCI Bus Trans Error Adr x00000000 MDPA Status Register x00000000 MDPA Status Register Data Not Valid MDPA Error Syndrome Reg x00000000 MDPA Syndrome Register Data Not Valid MDPB Status Register x00000000 MDPB Status Register Data Not Valid MDPB Error Syndrome Reg x00000000 MDPB Syndrome Register Data Not Valid ** IOD SUBPACKET -> ** IOD 1 Register Subpacket WHOAMI x0000033A Module Revision 0. VCTY ASIC Rev = 1 CPU = 0 This Bus Bridge Phy Addr x000000FBE0000000 IOD# 1 Dev Type & Rev Register x06000332 CAP Chip Revision: x00000002 B3040 Revision: x00000003 B3050 Revision: x00000003 AlphaServer 4100 MC-PCI Command Register x46460FF1 Module Self-Test Passed LED On. Delayed PCI Bus Reads Protocol: Enabled Bridge to PCI Transactions: Enabled Bridge REQUESTS 64 Bit Data Transactions Bridge ACCEPTS 64 Bit Data Transactions PCI Address Parity Check: Enabled MC Bus CMD/Addr Parity Check: Enabled MC Bus NXM Check: Enabled Check ALL Transactions for Errors Use MC_BMSK for 16 Byte Align Blk Mem Wrt Wrt PEND_NUM Threshold: 6. RD_TYPE Memory Prefetch Algorithm: Short RL_TYPE Mem Rd Line Prefetch Type: Medium RM_TYPE Mem Rd Multiple Cmd Type: Long ARB_MODE PCI Arbitration: Round Robin Mem Host Address Ext Reg x00000000 HAE Sparse Mem Adr<31:27> x00000000 IO Host Adr Ext Register x00000000 PCI Upper Adr Bits<31:25> x00000000 Interrupt Ctrl Register x00000003 Write Device Interrupt Info Struct:Enabled Interrupt Request x00800000 Interrupts asserted x00000000 Hard Error Interrupt Mask0 Register x00C50111 Interrupt Mask1 Register x00000000 MC Error Info Register 0 x148840E0 MC Bus Trans Addr<31:4>: 148840E0 MC Error Info Register 1 x800EDB00 MC bus trans addr <39:32> x00000000 MC Command is ReadMod1-Mem CPU1 Master at Time of Error Device ID: x00000003 MC error info valid CAP Error Register xA0000000 Uncorrectable ECC err det by MDPA MC error info latched PCI Bus Trans Error Adr xC00CBA80 MDPA Status Register x00000000 MDPA Status Register Data Not Valid MDPA Error Syndrome Reg x00000000 MDPA Syndrome Register Data Not Valid MDPB Status Register x00000000 MDPB Status Register Data Not Valid MDPB Error Syndrome Reg x00000000 MDPB Syndrome Register Data Not Valid PALcode Revision Palcode Rev: 1.21-26 ******************************** ENTRY 9 ******************************** Logging OS 2. Digital UNIX System Architecture 2. Alpha Event sequence number 2. Timestamp of occurrence 04-JUN-2001 19:53:16 Host name alpha System type register x00000016 Alpha 4000/1200 Series Number of CPUs (mpnum) x00000003 CPU logging event (mperr) x00000002 Event validity 1. O/S claims event is valid Event severity 5. Low Priority Entry type 203. LSM Note Events Type SWI Minor class 9. ASCII Message SWI Minor sub class 4. Informational ASCII Message LSM: Resynchronization of volume vol-rz8g in group rootdg started. ******************************** ENTRY 10 ******************************** Logging OS 2. Digital UNIX System Architecture 2. Alpha Event sequence number 1. Timestamp of occurrence 04-JUN-2001 19:54:28 Host name alpha System type register x00000016 Alpha 4000/1200 Series Number of CPUs (mpnum) x00000001 CPU logging event (mperr) x00000000 Event validity 1. O/S claims event is valid Event severity 5. Low Priority Entry type 300. Start-Up ASCII Message Type SWI Minor class 9. ASCII Message SWI Minor sub class 3. Startup ASCII Message Alpha boot: available memory from 0x4168000 to 0xbfff2000 Digital UNIX V4.0E (Rev. 1091); Wed May 17 17:32:00 EDT 2000 physical memory = 3072.00 megabytes. available memory = 3006.55 megabytes. using 11788 buffers containing 92.09 megabytes of memory Master cpu at slot 0. Firmware revision: 5.3 PALcode: Digital UNIX version 1.21 AlphaServer 4100 5/600 8MB pci1 at mcbus0 slot 5 psiop0 at pci1 slot 1 Loading SIOP: script c0000600, reg 7f9de00, data c000a518 scsi0 at psiop0 slot 0 rz5 at scsi0 target 5 lun 0 (LID=0) (DEC RRD46 (C) DEC 0557) isp0 at pci1 slot 2 isp0: QLOGIC ISP1040B/V2 isp0: Firmware revision 5.57 (loaded by console) isp0: Fast RAM timing enabled. scsi1 at isp0 slot 0 rz8 at scsi1 target 0 lun 0 (LID=1) (DEC RZ1CF-CF (C) DEC 1614) (Wide16) rz9 at scsi1 target 1 lun 0 (LID=2) (DEC RZ1CF-CF (C) DEC 1614) (Wide16) rz10 at scsi1 target 2 lun 0 (LID=3) (DEC RZ1CF-CF (C) DEC 1614) (Wide16) rz11 at scsi1 target 3 lun 0 (LID=4) (DEC RZ1CF-CF (C) DEC 1614) (Wide16) isp1 at pci1 slot 3 isp1: QLOGIC ISP1040B/V2 - Differential Mode isp1: Firmware revision 5.57 (loaded by console) isp1: Fast RAM timing enabled. scsi16 at isp1 slot 0 rz128 at scsi16 target 0 lun 0 (LID=5) (DEC HSZ70 V71Z) (Wide16) rzb128 at scsi16 target 0 lun 1 (LID=6) (DEC HSZ70 V71Z) (Wide16) rzc128 at scsi16 target 0 lun 2 (LID=7) (DEC HSZ70 V71Z) (Wide16) rzd128 at scsi16 target 0 lun 3 (LID=8) (DEC HSZ70 V71Z) (Wide16) rze128 at scsi16 target 0 lun 4 (LID=9) (DEC HSZ70 V71Z) (Wide16) rzf128 at scsi16 target 0 lun 5 (LID=10) (DEC HSZ70 V71Z) (Wide16) rzg128 at scsi16 target 0 lun 6 (LID=11) (DEC HSZ70 V71Z) (Wide16) rzh128 at scsi16 target 0 lun 7 (LID=12) (DEC HSZ70 V71Z) (Wide16) rz129 at scsi16 target 1 lun 0 (LID=13) (DEC HSZ70 V71Z) (Wide16) rzb129 at scsi16 target 1 lun 1 (LID=14) (DEC HSZ70CCL V71Z) (Wide16) rzf129 at scsi16 target 1 lun 5 (LID=18) (DEC HSZ70 V71Z) (Wide16) rzg129 at scsi16 target 1 lun 6 (LID=19) (DEC HSZ70 V71Z) (Wide16) rzh129 at scsi16 target 1 lun 7 (LID=20) (DEC HSZ70 V71Z) (Wide16) rz130 at scsi16 target 2 lun 0 (LID=21) (DEC HSZ70 V71Z) (Wide16) rzc130 at scsi16 target 2 lun 2 (LID=23) (DEC HSZ70 V71Z) (Wide16) rze130 at scsi16 target 2 lun 4 (LID=25) (DEC HSZ70 V71Z) (Wide16) rz131 at scsi16 target 3 lun 0 (LID=29) (DEC HSZ70 V71Z) (Wide16) rzc131 at scsi16 target 3 lun 2 (LID=31) (DEC HSZ70 V71Z) (Wide16) rze131 at scsi16 target 3 lun 4 (LID=33) (DEC HSZ70 V71Z) (Wide16) rzh131 at scsi16 target 3 lun 7 (LID=36) (DEC HSZ70 V71Z) (Wide16) tu0: DECchip 21143: Revision: 3.0 tu0: auto negotiation capable device tu0 at pci1 slot 4 tu0: DEC TULIP (10/100) Ethernet Interface, hardware address: 00-00-F8-09-91-C0 tu0: auto negotiation off: selecting 100BaseTX (UTP) port: half duplex gpc0 at eisa0 pci0 at mcbus0 slot 4 eisa0 at pci0 ace0 at eisa0 ace1 at eisa0 lp0 at eisa0 fdi0 at eisa0 fd0 at fdi0 unit 0 trio0 at pci0 slot 2 trio0: S3 Trio64V+ (SVGA) Plug-N-Play, 1.0 Mb psiop1 at pci0 slot 5 Loading SIOP: script c0006600, reg 3feff00, data c0012918 scsi3 at psiop1 slot 0 tz29 at scsi3 target 5 lun 0 (LID=37) (QUANTUM DLT7000 2255) (Wide16) Created FRU table binary error log packet lvm0: configured. lvm1: configured. kernel console: trio0 dli: configured ATM Subsystem configured with 4 restart threads ATM IFMP: configured i2c: Server Management Hardware Present clubase: configured ATM UNI 3.x signalling: configured ATM IP interface: configured LAN Emulation: configured ******************************** ENTRY 11 ******************************** Logging OS 2. Digital UNIX System Architecture 2. Alpha Event sequence number 0. Timestamp of occurrence 04-JUN-2001 19:54:28 Host name alpha System type register x00000016 Alpha 4000/1200 Series Number of CPUs (mpnum) x00000001 CPU logging event (mperr) x00000000 Event validity 1. O/S claims event is valid Event severity 5. Low Priority Entry type 110. Generalized Machine State Type SWI Minor class 3. System configuration ******************** FRU Table Header ****************** FRU Table Version x00000004 Major Revision 4. Minor Revision 0. ================ System Resource Subpacket =============== Length x016F Class 1. System Resource Subpacket Type 1. System Platform Rev 2. System Variation x0000000000000865 SysType Spec: AlphaServer 4100 Rack Graphics: NO Embedded Graphics Pwr Fail Restart: Restart Primary Proc PowerFail: Full Battery Backup Console: Embedded Console MultiProcessing: MultiProcessing Support Reset Reason x00000002 Software Requested Reset Number Environ Variables 11. Manufacturer Digital Model AlphaServer 4100 Serial Number NI85113847 Revision Level A01 Console Type Revision V5.3-1, 27-OCT-1998 11:16:38 Environmental Variables auto_action:BOOT boot_dev:dkb0.0.0.2.1 dkb100.1.0.2.1 bootdef_dev:dkb0.0.0.2.1 dkb100.1.0.2.1 booted_dev: boot_file: booted_file: boot_osflags:a booted_osflags: boot_reset:ON dump_dev: enable_audit:ON --------------------- FRU Subpacket ---------------------- Length x0060 Class 2. FRU Subpacket Type 1. Standard FRU Rev 2. Alphaserver 4x00 Specific FRU Location 0. Slot Name: System Motherboard Self Test Status x00000001 Self-Test Status NOT Available Manufacturer Digital Model AlphaServer 4100 Part Number 23803-01 Serial Number KA815KL173 Revision Level A01 Firmware RevLevel * NOT Logged * Self Test Information * NOT Logged * ================ System Resource Subpacket =============== Length x0061 Class 1. System Resource Subpacket Type 2. Processor Rev 3. Processor ID 0. ID of this Processor in Multiprocessor Sys Processor Family x00000030 Alpha AXP CPU State x00000000000001CC PA, Processor Available PP, Processor Present PV, PALCODE Valid PMV, PALCODE Memory Valid PL, PALCODE Loaded HALTREQ: Default AVAILABLE PALcode PALcode Image 1 x0004001200010113 Maximum CPUs 4. PALcode Revision OpenVMS PALcode V1.19-18 PALcode Image 2 x0004001A00020115 Maximum CPUs 4. PALcode Revision UNIX PALcode V1.21-26 Processor Type x0000000200000007 EV56 (21164A), Pass 2 Processor Variation x0000000000000007 VAX-FP, VAX floating point support IEEE-FP, IEEE floating point support PE, Processor eligible to become Primary Manufacturer Digital Serial Number AY84969938 Revision Level 1 ================ System Resource Subpacket =============== Length x0026 Class 1. System Resource Subpacket Type 7. Cache Rev 2. Cache Level 4. Secondary Cache Speed (ns) 0. Cache Size (kilobytes) 8192. Cache Available 8192. Cache Write Policy x0003 Write Back Cache Err Corr Scheme x0005 Single Bit ECC Cache Type x0005 Unified Cache Status x0003 Enabled --------------------- FRU Subpacket ---------------------- Length x005A Class 2. FRU Subpacket Type 1. Standard FRU Rev 2. Alphaserver 4x00 Specific FRU Location 2. Slot Name: CPU0 Self Test Status x00000002 FRU Passed Self-Test Manufacturer Digital Model 200000007 Part Number B3006-EB Serial Number AY84969938 Revision Level 1 Firmware RevLevel V3.0 Self Test Information * NOT Logged * ================ System Resource Subpacket =============== Length x0061 Class 1. System Resource Subpacket Type 2. Processor Rev 3. Processor ID 1. Processor Family x00000030 Alpha AXP CPU State x00000000000001CC PA, Processor Available PP, Processor Present PV, PALCODE Valid PMV, PALCODE Memory Valid PL, PALCODE Loaded HALTREQ: Default AVAILABLE PALcode PALcode Image 1 x0004001200010113 Maximum CPUs 4. PALcode Revision OpenVMS PALcode V1.19-18 PALcode Image 2 x0004001A00020115 Maximum CPUs 4. PALcode Revision UNIX PALcode V1.21-26 Processor Type x0000000200000007 EV56 (21164A), Pass 2 Processor Variation x0000000000000003 VAX-FP, VAX floating point support IEEE-FP, IEEE floating point support Manufacturer Digital Serial Number AY84956224 Revision Level 1 ================ System Resource Subpacket =============== Length x0026 Class 1. System Resource Subpacket Type 7. Cache Rev 2. Cache Level 4. Secondary Cache Speed (ns) 0. Cache Size (kilobytes) 8192. Cache Available 8192. Cache Write Policy x0003 Write Back Cache Err Corr Scheme x0005 Single Bit ECC Cache Type x0005 Unified Cache Status x0003 Enabled --------------------- FRU Subpacket ---------------------- Length x005A Class 2. FRU Subpacket Type 1. Standard FRU Rev 2. Alphaserver 4x00 Specific FRU Location 3. Slot Name: CPU1 Self Test Status x00000002 FRU Passed Self-Test Manufacturer Digital Model 200000007 Part Number B3006-EB Serial Number AY84956224 Revision Level 1 Firmware RevLevel V3.0 Self Test Information * NOT Logged * ================ System Resource Subpacket =============== Length x0061 Class 1. System Resource Subpacket Type 2. Processor Rev 3. Processor ID 2. Processor Family x00000030 Alpha AXP CPU State x00000000000001CC PA, Processor Available PP, Processor Present PV, PALCODE Valid PMV, PALCODE Memory Valid PL, PALCODE Loaded HALTREQ: Default AVAILABLE PALcode PALcode Image 1 x0004001200010113 Maximum CPUs 4. PALcode Revision OpenVMS PALcode V1.19-18 PALcode Image 2 x0004001A00020115 Maximum CPUs 4. PALcode Revision UNIX PALcode V1.21-26 Processor Type x0000000200000007 EV56 (21164A), Pass 2 Processor Variation x0000000000000003 VAX-FP, VAX floating point support IEEE-FP, IEEE floating point support Manufacturer Digital Serial Number AY01500635 Revision Level 1 ================ System Resource Subpacket =============== Length x0026 Class 1. System Resource Subpacket Type 7. Cache Rev 2. Cache Level 4. Secondary Cache Speed (ns) 0. Cache Size (kilobytes) 8192. Cache Available 8192. Cache Write Policy x0003 Write Back Cache Err Corr Scheme x0005 Single Bit ECC Cache Type x0005 Unified Cache Status x0003 Enabled --------------------- FRU Subpacket ---------------------- Length x005A Class 2. FRU Subpacket Type 1. Standard FRU Rev 2. Alphaserver 4x00 Specific FRU Location 6. Slot Name: CPU2 (4100) or IOD2/3 (4000) Self Test Status x00000002 FRU Passed Self-Test Manufacturer Digital Model 200000007 Part Number B3006-EB Serial Number AY01500635 Revision Level 1 Firmware RevLevel V3.0 Self Test Information * NOT Logged * ================ System Resource Subpacket =============== Length x0061 Class 1. System Resource Subpacket Type 2. Processor Rev 3. Processor ID 3. Processor Family x00000030 Alpha AXP CPU State x00000000000001CC PA, Processor Available PP, Processor Present PV, PALCODE Valid PMV, PALCODE Memory Valid PL, PALCODE Loaded HALTREQ: Default AVAILABLE PALcode PALcode Image 1 x0004001200010113 Maximum CPUs 4. PALcode Revision OpenVMS PALcode V1.19-18 PALcode Image 2 x0004001A00020115 Maximum CPUs 4. PALcode Revision UNIX PALcode V1.21-26 Processor Type x0000000200000007 EV56 (21164A), Pass 2 Processor Variation x0000000000000003 VAX-FP, VAX floating point support IEEE-FP, IEEE floating point support Manufacturer Digital Serial Number AY01003015 Revision Level 1 ================ System Resource Subpacket =============== Length x0026 Class 1. System Resource Subpacket Type 7. Cache Rev 2. Cache Level 4. Secondary Cache Speed (ns) 0. Cache Size (kilobytes) 8192. Cache Available 8192. Cache Write Policy x0003 Write Back Cache Err Corr Scheme x0005 Single Bit ECC Cache Type x0005 Unified Cache Status x0003 Enabled --------------------- FRU Subpacket ---------------------- Length x005A Class 2. FRU Subpacket Type 1. Standard FRU Rev 2. Alphaserver 4x00 Specific FRU Location 7. Slot Name: CPU3 (4100) or IOD2/3 (4000) Self Test Status x00000002 FRU Passed Self-Test Manufacturer Digital Model 200000007 Part Number B3006-EB Serial Number AY01003015 Revision Level 1 Firmware RevLevel V3.0 Self Test Information * NOT Logged * ================ System Resource Subpacket =============== Length x001D Class 1. System Resource Subpacket Type 3. Memory Rev 2. Total Memory Size x00000C00 Mbytes Installed: 3072. Memory Available x00000C00 Mbytes Available: 3072. Interleave Mode * NOT Logged * --------------------- FRU Subpacket ---------------------- Length x0052 Class 2. FRU Subpacket Type 2. Memory FRU Rev 2. Alphaserver 4x00 Specific FRU Location 0. Slot Name: MEM0L and MEM0H Self Test Status x00000001 Self-Test Status NOT Available Total Memory Size 2048. Mega Bytes (2 Modules) Module Size 1024. Mega Bytes (per Module) Memory Base Addr x0000000000000000 Memory Module Type x0000000000000002 EDO DRAM Manufacturer Digital Model * NOT Logged * Part Number * NOT Logged * Serial Number * NOT Logged * Revision Level * NOT Logged * Firmware RevLevel * NOT Logged * Self Test Information * NOT Logged * --------------------- FRU Subpacket ---------------------- Length x0052 Class 2. FRU Subpacket Type 2. Memory FRU Rev 2. Alphaserver 4x00 Specific FRU Location 1. Slot Name: MEM1L and MEM1H Self Test Status x00000001 Self-Test Status NOT Available Total Memory Size 1024. Mega Bytes (2 Modules) Module Size 512. Mega Bytes (per Module) Memory Base Addr x0000000080000000 Memory Module Type x0000000000000002 EDO DRAM Manufacturer Digital Model * NOT Logged * Part Number * NOT Logged * Serial Number * NOT Logged * Revision Level * NOT Logged * Firmware RevLevel * NOT Logged * Self Test Information * NOT Logged * ================ System Resource Subpacket =============== Length x0048 Class 1. System Resource Subpacket Type 4. System Bus Bridge Rev 2. Bridge Level x0001 PRIMARY Sys Bus Bridge: system -> bus_type Bus Type x0002 System Bus to PCI Bus Bridge Num Registers 10. This Bus Bridge Phy Addr x000000F9E0000000 IOD# 0 Dev Type & Rev Register x06008332 CAP Chip Revision: x00000002 B3040 Module Revision: x00000003 B3050 Module Revision: x00000003 B3050 Module Type: Left Hand PCI-EISA Bus Bridge Present on PCI Segment Device Class: Host Bus to PCI Bridge MC-PCI Command Register x46460FF1 Module Self-Test Passed LED On. Delayed PCI Bus Reads Protocol: Enabled Bridge to PCI Transactions: Enabled Bridge REQUESTS 64 Bit Data Transactions Bridge ACCEPTS 64 Bit Data Transactions PCI Address Parity Check: Enabled MC Bus CMD/Addr Parity Check: Enabled MC Bus NXM Check: Enabled Check ALL Transactions for Errors Use MC_BMSK for 16 Byte Align Blk Mem Wrt Wrt PEND_NUM Threshold: 6. RD_TYPE Memory Prefetch Algorithm: Short RL_TYPE Mem Rd Line Prefetch Type: Medium RM_TYPE Mem Rd Multiple Cmd Type: Long ARB_MODE PCI Arbitration: Round Robin Mem Host Address Ext Reg x00000000 HAE Sparse Mem Adr<31:27> x00000000 IO Host Adr Ext Register x00000000 PCI Upper Adr Bits<31:25> x00000000 Interrupt Ctrl Register x00000003 Write Device Interrupt Info Struct:Enabled Intr Target Dev Register x0000003A Intr Trgt-0 Dev ID(Octal) o72 Intr Trgt-1 Dev ID(Octal) o0 Intr Target Addr Register x00006000 Int Trgt Data Struct Ofst x00000000 Int Info Mem Trgt Pg Addr x00000006 Int Trgt Adr Ext Register x00000000 Int Info Mem Upr Adr Bits x00000000 Interrupt Mask0 Register x00250000 Interrupt Mask1 Register x00000000 ================ System Resource Subpacket =============== Length x00F8 Class 1. System Resource Subpacket Type 6. EISA Rev 2. - ESC Registers - 26. Revision ID x13 Unrecognized Mode Select Register x24 PIRQx# Mux/Map Ctrl<2:0>: x04 NMI on SERR(SysErr) Sig Disabled GPCS[2:0]# Functions Selected Config RAM Page Adr Gen Enabled MREQ[7:4]#/PIRQ[3:0]# Disabled BIOS Chip Select A x1F Low BIOS 1 Enabled Low BIOS 2 Enabled Low BIOS 3 Enabled Low BIOS 4 Enabled High BIOS Enabled BIOS Chip Select B x00 EISA Clock Divisor xC0 Clock Divisor = 4 (33.33MHz) Peripheral Chip Sel A x83 Real Time Clock Decode Enabled Keyboard Controller Decode Enabled Floppy/IDE Decode: 0b00 Primary Flpy Addr Rang Enabled Keyboard Ctlr Mapped to X-Bus Peripheral Chip Sel B xC4 Serial Port A Adr Decode: 0b00 Serial Port B Adr Decode: 0b01 LPT1 Port Decode Enabled PORT 92 Decode Enabled CRAM Decode Enabled EISA ID Byte 1 x10 EISA ID Byte 2 xA3 EISA ID Byte 3 x64 EISA ID Byte 4 x00 Scatter/Gather Base Addr x00 PIRQ Route CSR-0 x00 IRQ Routing Bits <06:00>: Reserved IRQx Routing of Interrupts Enabled PIRQ Route CSR-1 x00 IRQ Routing Bits <06:00>: Reserved IRQx Routing of Interrupts Enabled PIRQ Route CSR-2 x00 IRQ Routing Bits <06:00>: Reserved IRQx Routing of Interrupts Enabled PIRQ Route CSR-3 x00 IRQ Routing Bits <06:00>: Reserved IRQx Routing of Interrupts Enabled Gen Purp Chip Sel Addr 0 x0530 Gen Purp Chip Sel Mask 0 x01 Gen Purp Chip Sel Addr 1 x0026 Gen Purp Chip Sel Mask 1 x01 Gen Purp Chip Sel Addr 2 x0500 Gen Purp Chip Sel Mask 2 x1F Gen Purp Chip X-Bus Ctrl xFB GPCS 0 XBUSOE# Generates Enabled GPCS 1 XBUSOE# Generates Enabled -- PCEB Registers -- 17. Vendor/Device ID Code x04828086 Vendor: x8086 Intel Device: x0482 Intel 82375EB ** PCI-to-EISA BRIDGE ** PCI Command Low <7:0> x00000007 I/O Space Enabled Memory Space Enabled Bus Master Enabled Special Cycle Not Supported Mem Write Invalidate Not Supported VGA Palette Snoop Not Supported Parity Checking Disabled Wait State Control Not Supported PCI Command High <15:8> x00000000 SERR# Disabled Revision ID x00000015 Master Latency Timer x000000F8 Count: 31. PCI Control x00000060 Slow Sample Point Interrupt Acknowledge Enabled EISA-to-PCI Line Buf Enabled PCI Arbiter Control x0000009D Guaranteed Access Time Mod Enabled Bus Lock Disbled Bus Park Enabled Retries unmasked after 64 PCICLK's Auto-PEREQ# Control Enabled PCI Arbiter Priority Ctrl x000000F0 B0PRI = PCEBREQ# > REQ0# B1PRI = CPUREQ# > REQ3# B2PRI = Bank0 > Bank3 > Bank1 Bank 0 Rotate Control Enabled Bank 1 Rotate Control Enabled Bank 2 Rotate Control Enabled Bank 3 Rotate Control Enabled PCI Decode Control x00000020 Subtractive Decode (82375SB Only) IDEDC Positive Decode Disabled 8259C Positive Decode Enabled EISA-to-PCI Mem Attribute x00000001 Region 1 Buffered Access Region 2 Non-Buffered Access Region 3 Non-Buffered Access Region 4 Non-Buffered Access Mem Region 1 Addr <7:0> x00000000 Mem Region 1 Addr <15:8> x00000000 Mem Region 1 Addr <23:16> x000000FF Mem Region 1 Addr <31:24> x000000FF Number of EISA Devices - 4. ** Platform/Configuration Specific EISA SLOT Identification Slot 1. ** Device NOT Present Slot 2. ** Device NOT Present Slot 3. ** Device NOT Present Slot 4. ** Device NOT Present ================ System Resource Subpacket =============== Length x0058 Class 1. System Resource Subpacket Type 5. PCI Rev 1. PCI Device Registers ---- PCI Configuration Addr x000000F9C0010018 PCI: 0 Bus: 0 Device Number: 1 Vendor/Device ID Code x04828086 Vendor: x8086 Intel Device: x0482 Intel 82375EB ** PCI-to-EISA BRIDGE ** Command Register x0007 I/O Space Accesses Response: Enabled Memory Space Accesses Response: Enabled PCI Bus Master Capability; Enabled Monitor for Special Cycle Ops: DISABLED Generate Mem Wrt/Invalidate Cmds: DISABLED Parity Error Detection Response: *IGNORE* Wait Cycle Address/Data Stepping: DISABLED SERR# Sys Err Driver Capability: DISABLED Fast Back-to-Back to Many Target: DISABLED Status Register x0200 Device is 33 Mhz Capable. No Support for User Defineable Features. Fast Back-to-Back to Different Targets, Is Not Supported in Target Device. Device Select Timing: Medium. Device Revision x15 Device Class Code x000000 Zero's: Undefined or No Class Code Support Sys Cache Line Size x00 Latency Timer Value xF8 Header Type x00 Single Function Device Built-in Self Test CSR x00 Base Address Register 1 x00000000 Base Address Register 2 x00000000 Base Address Register 3 x00000000 Base Address Register 4 x00000000 Base Address Register 5 x00000000 Base Address Register 6 x00000000 Expansion Rom Base Addr x00000000 Interrupt Line Routing x00 Interrupt Pin Being Used x00 Min Bus Grant/Burst x00 Max Bus Latency x00 ================ System Resource Subpacket =============== Length x0058 Class 1. System Resource Subpacket Type 5. PCI Rev 1. PCI Device Registers ---- PCI Configuration Addr x000000F9C0020018 PCI: 0 Bus: 0 Device Number: 2 Vendor/Device ID Code x88115333 Vendor: x5333 S3 VISION INC. Device: x8811 Chip: 86C764 - S3 Vision Trio64/Trio32 v1 Command Register x0003 I/O Space Accesses Response: Enabled Memory Space Accesses Response: Enabled PCI Bus Master Capability; DISABLED Monitor for Special Cycle Ops: DISABLED Generate Mem Wrt/Invalidate Cmds: DISABLED Parity Error Detection Response: *IGNORE* Wait Cycle Address/Data Stepping: DISABLED SERR# Sys Err Driver Capability: DISABLED Fast Back-to-Back to Many Target: DISABLED Status Register x0200 Device is 33 Mhz Capable. No Support for User Defineable Features. Fast Back-to-Back to Different Targets, Is Not Supported in Target Device. Device Select Timing: Medium. Device Revision x54 Device Class Code x030000 Display Controller: VGA Compatible Ctlr Sys Cache Line Size x00 Latency Timer Value x00 Header Type x00 Single Function Device Built-in Self Test CSR x00 Base Address Register 1 x04000000 Base Address Register 2 x00000000 Base Address Register 3 x00000000 Base Address Register 4 x00000000 Base Address Register 5 x00000000 Base Address Register 6 x00000000 Expansion Rom Base Addr x03FF0000 Interrupt Line Routing x08 Interrupt Pin Being Used x01 Min Bus Grant/Burst x00 Max Bus Latency x00 ================ System Resource Subpacket =============== Length x0058 Class 1. System Resource Subpacket Type 5. PCI Rev 1. PCI Device Registers ---- PCI Configuration Addr x000000F9C0050018 PCI: 0 Bus: 0 Device Number: 5 Vendor/Device ID Code x00011000 Vendor: x1000 NCR Device: x0001 NCR 53C810 Fast/Narrow SCSI Controller Command Register x0147 I/O Space Accesses Response: Enabled Memory Space Accesses Response: Enabled PCI Bus Master Capability; Enabled Monitor for Special Cycle Ops: DISABLED Generate Mem Wrt/Invalidate Cmds: DISABLED Parity Error Detection Response: Normal Wait Cycle Address/Data Stepping: DISABLED SERR# Sys Err Driver Capability: Enabled Fast Back-to-Back to Many Target: DISABLED Status Register x0200 Device is 33 Mhz Capable. No Support for User Defineable Features. Fast Back-to-Back to Different Targets, Is Not Supported in Target Device. Device Select Timing: Medium. Device Revision x02 Device Class Code x010000 Mass Storage: SCSI Bus Controller Sys Cache Line Size x00 Latency Timer Value xFF Header Type x00 Single Function Device Built-in Self Test CSR x00 Base Address Register 1 x01FFFF01 Base Address Register 2 x03FEFF00 Base Address Register 3 x00000000 Base Address Register 4 x00000000 Base Address Register 5 x00000000 Base Address Register 6 x00000000 Expansion Rom Base Addr x00000000 Interrupt Line Routing x14 Interrupt Pin Being Used x01 Min Bus Grant/Burst x00 Max Bus Latency x00 ================ System Resource Subpacket =============== Length x0048 Class 1. System Resource Subpacket Type 4. System Bus Bridge Rev 2. Bridge Level x0001 PRIMARY Sys Bus Bridge: system -> bus_type Bus Type x0002 System Bus to PCI Bus Bridge Num Registers 10. This Bus Bridge Phy Addr x000000FBE0000000 IOD# 1 Dev Type & Rev Register x06000332 CAP Chip Revision: x00000002 B3040 Module Revision: x00000003 B3050 Module Revision: x00000003 B3050 Module Type: Left Hand Internal CAP Chip Arbiter: Enabled Device Class: Host Bus to PCI Bridge MC-PCI Command Register x46460FF1 Module Self-Test Passed LED On. Delayed PCI Bus Reads Protocol: Enabled Bridge to PCI Transactions: Enabled Bridge REQUESTS 64 Bit Data Transactions Bridge ACCEPTS 64 Bit Data Transactions PCI Address Parity Check: Enabled MC Bus CMD/Addr Parity Check: Enabled MC Bus NXM Check: Enabled Check ALL Transactions for Errors Use MC_BMSK for 16 Byte Align Blk Mem Wrt Wrt PEND_NUM Threshold: 6. RD_TYPE Memory Prefetch Algorithm: Short RL_TYPE Mem Rd Line Prefetch Type: Medium RM_TYPE Mem Rd Multiple Cmd Type: Long ARB_MODE PCI Arbitration: Round Robin Mem Host Address Ext Reg x00000000 HAE Sparse Mem Adr<31:27> x00000000 IO Host Adr Ext Register x00000000 PCI Upper Adr Bits<31:25> x00000000 Interrupt Ctrl Register x00000003 Write Device Interrupt Info Struct:Enabled Intr Target Dev Register x0000003A Intr Trgt-0 Dev ID(Octal) o72 Intr Trgt-1 Dev ID(Octal) o0 Intr Target Addr Register x00006004 Int Trgt Data Struct Ofst x00000001 Int Info Mem Trgt Pg Addr x00000006 Int Trgt Adr Ext Register x00000000 Int Info Mem Upr Adr Bits x00000000 Interrupt Mask0 Register x00000000 Interrupt Mask1 Register x00000000 ================ System Resource Subpacket =============== Length x0058 Class 1. System Resource Subpacket Type 5. PCI Rev 1. PCI Device Registers ---- PCI Configuration Addr x000000FBC0010018 PCI: 1 Bus: 0 Device Number: 1 Vendor/Device ID Code x00011000 Vendor: x1000 NCR Device: x0001 NCR 53C810 Fast/Narrow SCSI Controller Command Register x0147 I/O Space Accesses Response: Enabled Memory Space Accesses Response: Enabled PCI Bus Master Capability; Enabled Monitor for Special Cycle Ops: DISABLED Generate Mem Wrt/Invalidate Cmds: DISABLED Parity Error Detection Response: Normal Wait Cycle Address/Data Stepping: DISABLED SERR# Sys Err Driver Capability: Enabled Fast Back-to-Back to Many Target: DISABLED Status Register x0200 Device is 33 Mhz Capable. No Support for User Defineable Features. Fast Back-to-Back to Different Targets, Is Not Supported in Target Device. Device Select Timing: Medium. Device Revision x02 Device Class Code x010000 Mass Storage: SCSI Bus Controller Sys Cache Line Size x00 Latency Timer Value xFF Header Type x00 Single Function Device Built-in Self Test CSR x00 Base Address Register 1 x01FFFC01 Base Address Register 2 x07F9DE00 Base Address Register 3 x00000000 Base Address Register 4 x00000000 Base Address Register 5 x00000000 Base Address Register 6 x00000000 Expansion Rom Base Addr x00000000 Interrupt Line Routing x04 Interrupt Pin Being Used x01 Min Bus Grant/Burst x00 Max Bus Latency x00 ================ System Resource Subpacket =============== Length x0058 Class 1. System Resource Subpacket Type 5. PCI Rev 1. PCI Device Registers ---- PCI Configuration Addr x000000FBC0020018 PCI: 1 Bus: 0 Device Number: 2 Vendor/Device ID Code x10201077 Vendor: x1077 QLogic Device: x1020 QLogic ISP_1020A/1040A SCSI Ctrl Command Register x0147 I/O Space Accesses Response: Enabled Memory Space Accesses Response: Enabled PCI Bus Master Capability; Enabled Monitor for Special Cycle Ops: DISABLED Generate Mem Wrt/Invalidate Cmds: DISABLED Parity Error Detection Response: Normal Wait Cycle Address/Data Stepping: DISABLED SERR# Sys Err Driver Capability: Enabled Fast Back-to-Back to Many Target: DISABLED Status Register x0200 Device is 33 Mhz Capable. No Support for User Defineable Features. Fast Back-to-Back to Different Targets, Is Not Supported in Target Device. Device Select Timing: Medium. Device Revision x05 Device Class Code x010000 Mass Storage: SCSI Bus Controller Sys Cache Line Size x10 Latency Timer Value xF8 Header Type x00 Single Function Device Built-in Self Test CSR x00 Base Address Register 1 x01FFFD01 Base Address Register 2 x07F9E000 Base Address Register 3 x00000000 Base Address Register 4 x00000000 Base Address Register 5 x00000000 Base Address Register 6 x00000000 Expansion Rom Base Addr x07FA0000 Interrupt Line Routing x08 Interrupt Pin Being Used x01 Min Bus Grant/Burst x00 Max Bus Latency x00 ================ System Resource Subpacket =============== Length x0058 Class 1. System Resource Subpacket Type 5. PCI Rev 1. PCI Device Registers ---- PCI Configuration Addr x000000FBC0030018 PCI: 1 Bus: 0 Device Number: 3 Vendor/Device ID Code x10201077 Vendor: x1077 QLogic Device: x1020 QLogic ISP_1020A/1040A SCSI Ctrl Command Register x0147 I/O Space Accesses Response: Enabled Memory Space Accesses Response: Enabled PCI Bus Master Capability; Enabled Monitor for Special Cycle Ops: DISABLED Generate Mem Wrt/Invalidate Cmds: DISABLED Parity Error Detection Response: Normal Wait Cycle Address/Data Stepping: DISABLED SERR# Sys Err Driver Capability: Enabled Fast Back-to-Back to Many Target: DISABLED Status Register x0200 Device is 33 Mhz Capable. No Support for User Defineable Features. Fast Back-to-Back to Different Targets, Is Not Supported in Target Device. Device Select Timing: Medium. Device Revision x05 Device Class Code x010000 Mass Storage: SCSI Bus Controller Sys Cache Line Size x10 Latency Timer Value xF8 Header Type x00 Single Function Device Built-in Self Test CSR x00 Base Address Register 1 x01FFFE01 Base Address Register 2 x07F9F000 Base Address Register 3 x00000000 Base Address Register 4 x00000000 Base Address Register 5 x00000000 Base Address Register 6 x00000000 Expansion Rom Base Addr x07FB0000 Interrupt Line Routing x0C Interrupt Pin Being Used x01 Min Bus Grant/Burst x00 Max Bus Latency x00 ================ System Resource Subpacket =============== Length x0058 Class 1. System Resource Subpacket Type 5. PCI Rev 1. PCI Device Registers ---- PCI Configuration Addr x000000FBC0040018 PCI: 1 Bus: 0 Device Number: 4 Vendor/Device ID Code x00191011 Vendor: x1011 Digital Equipment Corp. Device: x0019 DC21143 TWINNET PCI/CardBus 10/100 Mbit, Dual Ethernet Controller Command Register x0147 I/O Space Accesses Response: Enabled Memory Space Accesses Response: Enabled PCI Bus Master Capability; Enabled Monitor for Special Cycle Ops: DISABLED Generate Mem Wrt/Invalidate Cmds: DISABLED Parity Error Detection Response: Normal Wait Cycle Address/Data Stepping: DISABLED SERR# Sys Err Driver Capability: Enabled Fast Back-to-Back to Many Target: DISABLED Status Register x0280 Device is 33 Mhz Capable. No Support for User Defineable Features. Fast Back-to-Back to Different Targets, Is Supported in Target Device. Device Select Timing: Medium. Device Revision x30 Device Class Code x020000 Network Controller: Ethernet Controller Sys Cache Line Size x10 Latency Timer Value xFF Header Type x00 Single Function Device Built-in Self Test CSR x00 Base Address Register 1 x01FFFF01 Base Address Register 2 x07F9DF00 Base Address Register 3 x00000000 Base Address Register 4 x00000000 Base Address Register 5 x00000000 Base Address Register 6 x00000000 Expansion Rom Base Addr x07FC0000 Interrupt Line Routing x10 Interrupt Pin Being Used x01 Min Bus Grant/Burst x14 Max Bus Latency x28 --------------------- FRU Subpacket ---------------------- Length x004F Class 2. FRU Subpacket Type 1. Standard FRU Rev 2. Alphaserver 4x00 Specific FRU Location 5. Slot Name: IOD0/1 Self Test Status x00000002 FRU Passed Self-Test Manufacturer Digital Model 0 Part Number B3040-AA Serial Number KA729YMJBB Revision Level 32 Firmware RevLevel * NOT Logged * Self Test Information * NOT Logged * --------------------- FRU Subpacket ---------------------- Length x0052 Class 2. FRU Subpacket Type 1. Standard FRU Rev 2. Alphaserver 4x00 Specific FRU Location 10. B3050 Module (Left Hand) Self Test Status x00000002 FRU Passed Self-Test Manufacturer Digital Model 0 Part Number B3052-AA Serial Number KA818NW727 Revision Level 3 Firmware RevLevel V5.3 Self Test Information * NOT Logged * ================ System Resource Subpacket =============== Length x0028 Class 1. System Resource Subpacket Type 8. Power Rev 2. Number of Elements 2. Element Type x0001 DC Power Supply ID No 0. Status x00000001 OK Element Type x0001 DC Power Supply ID No 2. Status x00000001 OK ================ System Resource Subpacket =============== Length x0F04 Class 1. System Resource Subpacket Type 10. System Initialization Log Rev 1. System Init Log 23:35.14 initializing overlays 23:35.14 XDELTA not enabled. 23:35.14 initializing flash index 23:35.14 hf_init 23:35.14 flash index count = 68, adr = cec14 23:35.14 flash seq_minor = 10003, var_major = 560005 23:35.14 starting console on CPU 0 23:35.14 initializing file system 23:35.14 DDB Startup, phase = 0 23:35.14 DDB Startup nl 23:35.14 DDB Startup rd 23:35.14 DDB Startup buf 23:35.14 DDB Startup flash 23:35.14 DDB Startup sym 23:35.14 initializing timer data structures 23:35.14 lowering IPL 23:35.15 CPU 0 speed is 1.67 ns (599MHz) 23:35.15 DDB Startup, phase = 1 23:35.15 DDB Startup tt 23:35.15 DDB Startup combo 23:35.15 DDB Startup pmem 23:35.15 DDB Startup examine 23:35.15 DDB Startup esc_nvram 23:35.15 DDB Startup nvram 23:35.15 access NVRAM 23:35.15 DDB Startup iic 23:35.15 DDB Startup sable_ocp 23:35.15 DDB Startup toy 23:35.15 slot 7 - CPU 23:35.15 slot 6 - CPU 23:35.15 slot 5 IOD (6000) - hose 1 23:35.15 slot 4 IOD (6008) - hose 0 23:35.15 slot 3 - CPU 23:35.15 slot 2 - CPU 23:35.15 slot 1 - MEM 23:35.15 Loading startup overlays 23:35.15 DDB Startup, phase = 2 23:35.15 DDB Startup ev 23:35.15 entering idle loop 23:35.15 Loading start2 overlays 23:35.16 DDB Startup, phase = 3 23:35.16 DDB Startup el 23:35.16 DDB Startup vmem 23:35.16 DDB Startup ev5_ipr 23:35.16 DDB Startup gpr 23:35.16 DDB Startup fpr 23:35.16 DDB Startup pt 23:35.16 DDB Startup ps 23:35.16 DDB Startup pi 23:35.16 DDB Startup tee 23:35.16 DDB Startup decode 23:35.16 memzone: base = 1000000, mz_size = 7f000000 23:35.16 halt code = 34 23:35.16 PC = 1d8 23:35.16 starting console on CPU 1 23:35.16 lowering IPL 23:35.16 halt code = 34 23:35.16 PC = 1d8 23:35.16 starting console on CPU 2 23:35.16 lowering IPL 23:35.16 halt code = 34 23:35.16 PC = 1d8 23:35.16 starting console on CPU 3 23:35.16 lowering IPL 23:35.16 CPU 1 speed is 1.67 ns (599MHz) 23:35.16 entering idle loop 23:35.16 CPU 2 speed is 1.67 ns (599MHz) 23:35.16 CPU 3 speed is 1.67 ns (599MHz) 23:35.16 entering idle loop 23:35.16 entering idle loop 23:35.24 Executing iod_diag on device iod0 23:35.25 iod0 passed power-up tests 23:35.25 Executing iod_diag on device iod1 23:35.25 iod1 passed power-up tests 23:35.25 Executing pceb_diag 23:35.26 pceb passed power-up tests 23:35.26 Executing esc_diag 23:35.26 esc passed power-up tests 23:35.26 Executing ds1287_diag 23:35.26 toy passed power-up tests 23:35.26 Executing combo_diag 23:35.27 combo passed power-up tests 23:35.27 Executing ncr810_diag 23:35.27 n810 passed power-up tests 23:35.27 Initializing VGA 23:35.27 Starting Bios Emulator 23:35.27 Loading X86 & X86A 23:35.32 Created x86_process: pid 15 23:35.34 Completed Bios Emulation, status = 0 23:35.34 KBD h/s/b/f/c/dev/vect 0/0/1/1/0/11fb80/81 23:35.34 MOUSE h/s/b/f/c/dev/vect 0/0/1/2/0/11fca0/8c 23:35.34 initializing keyboard 23:35.36 kbd test passed 23:35.36 mouse test passed 23:35.36 Initialize VGA hardware 23:35.36 Stopping X86 Bios 23:35.36 Completed VGA 23:35.36 resetting the SCSI bus on pka0.7.0.1.1 23:35.37 port pka0.7.0.1.1 initialized, scripts are at 1287e0 23:35.38 resetting the SCSI bus on pkb0.7.0.2.1 23:35.38 clearing interrupt vector 000000b8 23:35.38 free all semaphores 23:35.38 free all dynamic memory 23:35.39 resetting the SCSI bus on pkc0.7.0.3.1 23:35.39 clearing interrupt vector 000000bc 23:35.39 free all semaphores 23:35.39 free all dynamic memory 23:35.40 resetting the SCSI bus on pkd0.7.0.5.0 23:35.41 port pkd0.7.0.5.0 initialized, scripts are at 12adc0 23:35.42 Created device: dkb0.0.0.2.1 23:35.43 resetting the SCSI bus on pkb0.7.0.2.1 23:35.44 sense key = 'Unit Attention' (29|02) from dkb0.0.0.2.1 23:35.45 breaking virtual connection with sb 00126700 23:35.45 clearing interrupt vector 000000b8 23:35.45 free all semaphores 23:35.45 free all dynamic memory ******************************** ENTRY 12 ******************************** Logging OS 2. Digital UNIX System Architecture 2. Alpha Event sequence number 4. Timestamp of occurrence 04-JUN-2001 19:51:02 Host name alpha System type register x00000016 Alpha 4000/1200 Series Number of CPUs (mpnum) x00000004 CPU logging event (mperr) x00000003 Event validity 1. O/S claims event is valid Event severity 1. Severe Priority Entry type 302. ASCII Panic Message Type SWI Minor class 9. ASCII Message SWI Minor sub class 1. Panic ASCII Message panic (cpu 3): Processor Machine Check ******************************** ENTRY 13 ******************************** Logging OS 2. Digital UNIX System Architecture 2. Alpha Event sequence number 3. Timestamp of occurrence 04-JUN-2001 19:51:02 Host name alpha System type register x00000016 Alpha 4000/1200 Series Number of CPUs (mpnum) x00000004 CPU logging event (mperr) x00000003 Event validity 1. O/S claims event is valid Event severity 1. Severe Priority Entry type 100. CPU Machine Check Errors CPU Minor class 1. Machine check (670 entry) Software Flags x0000000300000000 IOD 0 Register Subpkt Pres IOD 1 Register Subpkt Pres Active CPUs x0000000F Hardware Rev x00000000 System Serial Number NI85113847 Module Serial Number Module Type x0000 System Revision x00000000 * MCHK 670 Regs * Flags: x00000000 PCI Mask x0000 Machine Check Reason x0098 Fatal Alpha Chip Detected Hard Error PAL SHADOW REG 0 x0000000000000000 PAL SHADOW REG 1 x0000000000000000 PAL SHADOW REG 2 x0000000000000000 PAL SHADOW REG 3 x0000000000000000 PAL SHADOW REG 4 x0000000000000000 PAL SHADOW REG 5 x0000000000000000 PAL SHADOW REG 6 x0000000000000000 PAL SHADOW REG 7 x0000000000000000 PALTEMP0 xFFFFFFFFFFFFFFFF PALTEMP1 x000000000000001F PALTEMP2 xFFFFFC0000531010 PALTEMP3 x0000000000005588 PALTEMP4 x000000000000001F PALTEMP5 x0000000000000020 PALTEMP6 x0000000000000000 PALTEMP7 xFFFFFC0000530930 PALTEMP8 x1F1E171515020100 PALTEMP9 xFFFFFC0000530D50 PALTEMP10 x000003FF800D6404 PALTEMP11 xFFFFFC0000530BB0 PALTEMP12 xFFFFFC0000530F80 PALTEMP13 x0000000000006FC0 PALTEMP14 x0000000000000000 PALTEMP15 x00000000000049BC PALTEMP16 x0000009806700301 PALTEMP17 x0000000000000000 PALTEMP18 x00000001400DE128 PALTEMP19 xFFFFFFFE9C127A38 PALTEMP20 x0000000090804000 PALTEMP21 xFFFFFC0000530FB0 PALTEMP22 xFFFFFC0000720A50 PALTEMP23 x000000009A85DA38 Exception Address Reg x000003FF800D6404 Native-mode Instruction Exception PC x000000FFE0035901 Exception Summary Reg x0000000000000000 Exception Mask Reg x0000000000000000 PAL Base Address Reg x0000000000014000 Base Addr for PALcode: x0000000000000005 Interrupt Summary Reg x0000000000000000 AST Requests 3-0: x0000000000000000 IBOX Ctrl and Status Reg x000000C164020000 Timeout Counter Bit Clear. IBOX Timeout Counter Enabled. Floating Point Instr's May be Issued. PAL Shadow Registers Enabled. Correctable Error Interrupts Enabled. ICACHE BIST (Self Test) Was Successful. TEST_STATUS_H Pin Asserted Icache Par Err Stat Reg x0000000000000000 Dcache Par Err Stat Reg x0000000000000000 Virtual Address Reg x00000001400EA000 Memory Mgmt Flt Sts Reg x00000000000149D0 If Err, Reference Resulted in DTB Miss Fault Inst RA Field: x0000000000000007 Fault Inst Opcode: x0000000000000029 Scache Address Reg xFFFFFF0000018FEF Scache Status Reg x0000000000000000 Bcache Tag Address Reg xFFFFFF809D8FBFFF Last Bcache Access Resulted in a Hit. Value of Parity Bit for Tag Control Status Bits Dirty, Shared & Valid is Set. Value of Tag Control Dirty Bit is Clear. Value of Tag Control Shared Bit is Set. Value of Tag Control Valid Bit is Set. Value of Parity Bit Covering Tag Store Address Bits is Set. Tag Address<38:20> Is: x00000000000009D8 Ext Interface Address Reg xFFFFFF009D8840FF Fill Syndrome Reg x00000000000000F3 Ext Interface Status Reg xFFFFFFF105FFFFFF UNCORRECTABLE ECC ERROR Error Occurred During D-ref Fill LD LOCK xFFFFFF009D09A08F ** IOD SUBPACKET -> ** IOD 0 Register Subpacket WHOAMI x0000033F Module Revision 0. VCTY ASIC Rev = 1 CPU = 3 This Bus Bridge Phy Addr x000000F9E0000000 IOD# 0 Dev Type & Rev Register x06008332 CAP Chip Revision: x00000002 B3040 Revision: x00000003 B3050 Revision: x00000003 AlphaServer 4100 MC-PCI Command Register x46460FF1 Module Self-Test Passed LED On. Delayed PCI Bus Reads Protocol: Enabled Bridge to PCI Transactions: Enabled Bridge REQUESTS 64 Bit Data Transactions Bridge ACCEPTS 64 Bit Data Transactions PCI Address Parity Check: Enabled MC Bus CMD/Addr Parity Check: Enabled MC Bus NXM Check: Enabled Check ALL Transactions for Errors Use MC_BMSK for 16 Byte Align Blk Mem Wrt Wrt PEND_NUM Threshold: 6. RD_TYPE Memory Prefetch Algorithm: Short RL_TYPE Mem Rd Line Prefetch Type: Medium RM_TYPE Mem Rd Multiple Cmd Type: Long ARB_MODE PCI Arbitration: Round Robin Mem Host Address Ext Reg x00000000 HAE Sparse Mem Adr<31:27> x00000000 IO Host Adr Ext Register x00000000 PCI Upper Adr Bits<31:25> x00000000 Interrupt Ctrl Register x00000003 Write Device Interrupt Info Struct:Enabled Interrupt Request x00000000 Interrupts asserted x00000000 Interrupt Mask0 Register x00C51000 Interrupt Mask1 Register x00000000 MC Error Info Register 0 xE0000000 MC Bus Trans Addr<31:4>: E0000000 MC Error Info Register 1 x000E88FD MC bus trans addr <39:32> x000000FD MC Command is Read0-IO CPU0 Master at Time of Error Device ID 2 x00000002 CAP Error Register x00000000 PCI Bus Trans Error Adr x00000000 MDPA Status Register x00000000 MDPA Status Register Data Not Valid MDPA Error Syndrome Reg x00000000 MDPA Syndrome Register Data Not Valid MDPB Status Register x00000000 MDPB Status Register Data Not Valid MDPB Error Syndrome Reg x00000000 MDPB Syndrome Register Data Not Valid ** IOD SUBPACKET -> ** IOD 1 Register Subpacket WHOAMI x0000033F Module Revision 0. VCTY ASIC Rev = 1 CPU = 3 This Bus Bridge Phy Addr x000000FBE0000000 IOD# 1 Dev Type & Rev Register x06000332 CAP Chip Revision: x00000002 B3040 Revision: x00000003 B3050 Revision: x00000003 AlphaServer 4100 MC-PCI Command Register x46460FF1 Module Self-Test Passed LED On. Delayed PCI Bus Reads Protocol: Enabled Bridge to PCI Transactions: Enabled Bridge REQUESTS 64 Bit Data Transactions Bridge ACCEPTS 64 Bit Data Transactions PCI Address Parity Check: Enabled MC Bus CMD/Addr Parity Check: Enabled MC Bus NXM Check: Enabled Check ALL Transactions for Errors Use MC_BMSK for 16 Byte Align Blk Mem Wrt Wrt PEND_NUM Threshold: 6. RD_TYPE Memory Prefetch Algorithm: Short RL_TYPE Mem Rd Line Prefetch Type: Medium RM_TYPE Mem Rd Multiple Cmd Type: Long ARB_MODE PCI Arbitration: Round Robin Mem Host Address Ext Reg x00000000 HAE Sparse Mem Adr<31:27> x00000000 IO Host Adr Ext Register x00000000 PCI Upper Adr Bits<31:25> x00000000 Interrupt Ctrl Register x00000003 Write Device Interrupt Info Struct:Enabled Interrupt Request x00000000 Interrupts asserted x00000000 Interrupt Mask0 Register x00C50111 Interrupt Mask1 Register x00000000 MC Error Info Register 0 xE0000000 MC Bus Trans Addr<31:4>: E0000000 MC Error Info Register 1 x000E88FD MC bus trans addr <39:32> x000000FD MC Command is Read0-IO CPU0 Master at Time of Error Device ID 2 x00000002 CAP Error Register x00000000 PCI Bus Trans Error Adr x00000000 MDPA Status Register x00000000 MDPA Status Register Data Not Valid MDPA Error Syndrome Reg x00000000 MDPA Syndrome Register Data Not Valid MDPB Status Register x00000000 MDPB Status Register Data Not Valid MDPB Error Syndrome Reg x00000000 MDPB Syndrome Register Data Not Valid PALcode Revision Palcode Rev: 1.21-26 ... DECevent V2.8 ******************************** ENTRY 37 ******************************** Logging OS 2. Digital UNIX System Architecture 2. Alpha Event sequence number 22. Timestamp of occurrence 04-JUN-2001 19:16:44 Host name alpha System type register x00000016 Alpha 4000/1200 Series Number of CPUs (mpnum) x00000004 CPU logging event (mperr) x00000000 Event validity 1. O/S claims event is valid Event severity 5. Low Priority Entry type 100. CPU Machine Check Errors CPU Minor class 4. 620 System Correctable Error Software Flags x0000000000000000 Active CPUs x0000000F Hardware Rev x00000000 System Serial Number NI85113847 Module Serial Number Module Type x0000 System Revision x00000000 Machine Check Reason x0204 IOD Detected Soft Error Ext Interface Status Reg x0000000000000000 Register Contents Not Valid For This Error Ext Interface Address Reg x0000000000000000 Register Contents Not Valid For This Error Fill Syndrome Reg x0000000000000000 Register Contents Not Valid For This Error Interrupt Summary Reg x0000000000000000 Register Contents Not Valid For This Error WHOAMI x00000000 Register Contents Not Valid For This Error --IOD REGISTERS FOLLOW-- This Bus Bridge Phy Addr x000000FBE0000000 IOD# 1 Dev Type & Rev Register x06000332 CAP Chip Revision: x00000002 B3040 Revision: x00000003 B3050 Revision: x00000003 AlphaServer 4100 MC Error Info Register 0 x998842C0 MC Bus Trans Addr<31:4>: 998842C0 MC Error Info Register 1 x800FD600 MC bus trans addr <39:32> x00000000 MC Command is WriteBack Mem CPU3 OR IOD3 Master at Time of Error Device ID: x00000007 MC error info valid CAP Error Register x89000000 Error Detected but Not Logged Correctable ECC err det by MDPA MC error info latched MDPA Status Register x00000000 MDPA Status Register Data Not Valid MDPA Error Syndrome Reg x00000000 MDPA Syndrome Register Data Not Valid MDPB Status Register x00000000 MDPB Status Register Data Not Valid MDPB Error Syndrome Reg x00000000 MDPB Syndrome Register Data Not Valid PALcode Revision Palcode Rev: 1.21-26 ******************************** ENTRY 38 ******************************** Logging OS 2. Digital UNIX System Architecture 2. Alpha Event sequence number 21. Timestamp of occurrence 04-JUN-2001 19:16:44 Host name alpha System type register x00000016 Alpha 4000/1200 Series Number of CPUs (mpnum) x00000004 CPU logging event (mperr) x00000000 Event validity 1. O/S claims event is valid Event severity 5. Low Priority Entry type 100. CPU Machine Check Errors CPU Minor class 4. 620 System Correctable Error Software Flags x0000000000000000 Active CPUs x0000000F Hardware Rev x00000000 System Serial Number NI85113847 Module Serial Number Module Type x0000 System Revision x00000000 Machine Check Reason x0204 IOD Detected Soft Error Ext Interface Status Reg x0000000000000000 Register Contents Not Valid For This Error Ext Interface Address Reg x0000000000000000 Register Contents Not Valid For This Error Fill Syndrome Reg x0000000000000000 Register Contents Not Valid For This Error Interrupt Summary Reg x0000000000000000 Register Contents Not Valid For This Error WHOAMI x00000000 Register Contents Not Valid For This Error --IOD REGISTERS FOLLOW-- This Bus Bridge Phy Addr x000000F9E0000000 IOD# 0 Dev Type & Rev Register x06008332 CAP Chip Revision: x00000002 B3040 Revision: x00000003 B3050 Revision: x00000003 AlphaServer 4100 MC Error Info Register 0 x998842C0 MC Bus Trans Addr<31:4>: 998842C0 MC Error Info Register 1 x800FD600 MC bus trans addr <39:32> x00000000 MC Command is WriteBack Mem CPU3 OR IOD3 Master at Time of Error Device ID: x00000007 MC error info valid CAP Error Register x89000000 Error Detected but Not Logged Correctable ECC err det by MDPA MC error info latched MDPA Status Register x00000000 MDPA Status Register Data Not Valid MDPA Error Syndrome Reg x00000000 MDPA Syndrome Register Data Not Valid MDPB Status Register x00000000 MDPB Status Register Data Not Valid MDPB Error Syndrome Reg x00000000 MDPB Syndrome Register Data Not Valid PALcode Revision Palcode Rev: 1.21-26 ******************************** ENTRY 39 ******************************** Logging OS 2. Digital UNIX System Architecture 2. Alpha Event sequence number 20. Timestamp of occurrence 04-JUN-2001 19:14:23 Host name alpha System type register x00000016 Alpha 4000/1200 Series Number of CPUs (mpnum) x00000004 CPU logging event (mperr) x00000002 Event validity 1. O/S claims event is valid Event severity 5. Low Priority Entry type 310. Time Stamp ** Error during CTR processing of EVT seg - Canonical buffer dump follows Entry# (record in file) 0. Canonical buff size 32736. Canonical event size 258. Canonical Event-Buffer: 15--<-12 11--<-08 07--<-04 03--<-00 :Byte Order 0000: 00000027 00000000 00000000 00000003 *............'...* 0010: 00000202 4E454720 33317646 534F0001 *..OSFv13 GEN....* 0020: 00000000 00000000 00000000 00000000 *................* 0030: 00140000 00000000 00000000 00000000 *................* 0040: 30303332 34313931 34303630 31303032 *2001060419142300* 0050: 00000000 00000000 00000020 20202020 * ...........* 0060: 00000000 00000000 00616870 6C610000 *..alpha.........* 0070: 00000000 00000000 00000000 00000000 *................* 0080: 33317646 534F0001 00000000 00000000 *..........OSFv13* 0090: 000000FF 00000016 00000000 55504320 * CPU............* 00A0: 00000000 00000000 00000002 00000004 *................* 00B0: 00000000 00000000 00000000 00000000 *................* 00C0: 00000000 00000000 00000000 00000000 *................* 00D0: 00000000 00000000 00000000 00000000 *................* 00E0: 00000000 00000000 00000000 00000000 *................* 00F0: 00000000 00000000 00000000 00000700 *................* 0100: 00000001 * ....* ******************************** ENTRY 40 ******************************** Logging OS 2. Digital UNIX System Architecture 2. Alpha Event sequence number 19. Timestamp of occurrence 04-JUN-2001 19:04:23 Host name alpha System type register x00000016 Alpha 4000/1200 Series Number of CPUs (mpnum) x00000004 CPU logging event (mperr) x00000000 Event validity 1. O/S claims event is valid Event severity 5. Low Priority Entry type 100. CPU Machine Check Errors CPU Minor class 4. 620 System Correctable Error Software Flags x0000000000000000 Active CPUs x0000000F Hardware Rev x00000000 System Serial Number NI85113847 Module Serial Number Module Type x0000 System Revision x00000000 Machine Check Reason x0204 IOD Detected Soft Error Ext Interface Status Reg x0000000000000000 Register Contents Not Valid For This Error Ext Interface Address Reg x0000000000000000 Register Contents Not Valid For This Error Fill Syndrome Reg x0000000000000000 Register Contents Not Valid For This Error Interrupt Summary Reg x0000000000000000 Register Contents Not Valid For This Error WHOAMI x00000000 Register Contents Not Valid For This Error --IOD REGISTERS FOLLOW-- This Bus Bridge Phy Addr x000000FBE0000000 IOD# 1 Dev Type & Rev Register x06000332 CAP Chip Revision: x00000002 B3040 Revision: x00000003 B3050 Revision: x00000003 AlphaServer 4100 MC Error Info Register 0 xB20840E0 MC Bus Trans Addr<31:4>: B20840E0 MC Error Info Register 1 x800FD600 MC bus trans addr <39:32> x00000000 MC Command is WriteBack Mem CPU3 OR IOD3 Master at Time of Error Device ID: x00000007 MC error info valid CAP Error Register x89000000 Error Detected but Not Logged Correctable ECC err det by MDPA MC error info latched MDPA Status Register x00000000 MDPA Status Register Data Not Valid MDPA Error Syndrome Reg x00000000 MDPA Syndrome Register Data Not Valid MDPB Status Register x00000000 MDPB Status Register Data Not Valid MDPB Error Syndrome Reg x00000000 MDPB Syndrome Register Data Not Valid PALcode Revision Palcode Rev: 1.21-26 ******************************** ENTRY 41 ******************************** Logging OS 2. Digital UNIX System Architecture 2. Alpha Event sequence number 18. Timestamp of occurrence 04-JUN-2001 19:04:23 Host name alpha System type register x00000016 Alpha 4000/1200 Series Number of CPUs (mpnum) x00000004 CPU logging event (mperr) x00000000 Event validity 1. O/S claims event is valid Event severity 5. Low Priority Entry type 100. CPU Machine Check Errors CPU Minor class 4. 620 System Correctable Error Software Flags x0000000000000000 Active CPUs x0000000F Hardware Rev x00000000 System Serial Number NI85113847 Module Serial Number Module Type x0000 System Revision x00000000 Machine Check Reason x0204 IOD Detected Soft Error Ext Interface Status Reg x0000000000000000 Register Contents Not Valid For This Error Ext Interface Address Reg x0000000000000000 Register Contents Not Valid For This Error Fill Syndrome Reg x0000000000000000 Register Contents Not Valid For This Error Interrupt Summary Reg x0000000000000000 Register Contents Not Valid For This Error WHOAMI x00000000 Register Contents Not Valid For This Error --IOD REGISTERS FOLLOW-- This Bus Bridge Phy Addr x000000F9E0000000 IOD# 0 Dev Type & Rev Register x06008332 CAP Chip Revision: x00000002 B3040 Revision: x00000003 B3050 Revision: x00000003 AlphaServer 4100 MC Error Info Register 0 xB20840E0 MC Bus Trans Addr<31:4>: B20840E0 MC Error Info Register 1 x800FD600 MC bus trans addr <39:32> x00000000 MC Command is WriteBack Mem CPU3 OR IOD3 Master at Time of Error Device ID: x00000007 MC error info valid CAP Error Register x89000000 Error Detected but Not Logged Correctable ECC err det by MDPA MC error info latched MDPA Status Register x00000000 MDPA Status Register Data Not Valid MDPA Error Syndrome Reg x00000000 MDPA Syndrome Register Data Not Valid MDPB Status Register x00000000 MDPB Status Register Data Not Valid MDPB Error Syndrome Reg x00000000 MDPB Syndrome Register Data Not Valid PALcode Revision Palcode Rev: 1.21-26 ******************************** ENTRY 42 ******************************** Logging OS 2. Digital UNIX System Architecture 2. Alpha Event sequence number 17. Timestamp of occurrence 04-JUN-2001 19:01:13 Host name alpha System type register x00000016 Alpha 4000/1200 Series Number of CPUs (mpnum) x00000004 CPU logging event (mperr) x00000003 Event validity 1. O/S claims event is valid Event severity 5. Low Priority Entry type 310. Time Stamp ** Error during CTR processing of EVT seg - Canonical buffer dump follows Entry# (record in file) 0. Canonical buff size 32736. Canonical event size 258. Canonical Event-Buffer: 15--<-12 11--<-08 07--<-04 03--<-00 :Byte Order 0000: 0000002A 00000000 00000000 00000003 *............*...* 0010: 00000202 4E454720 33317646 534F0001 *..OSFv13 GEN....* 0020: 00000000 00000000 00000000 00000000 *................* 0030: 00110000 00000000 00000000 00000000 *................* 0040: 30303331 31303931 34303630 31303032 *2001060419011300* 0050: 00000000 00000000 00000020 20202020 * ...........* 0060: 00000000 00000000 00616870 6C610000 *..alpha.........* 0070: 00000000 00000000 00000000 00000000 *................* 0080: 33317646 534F0001 00000000 00000000 *..........OSFv13* 0090: 000000FF 00000016 00000000 55504320 * CPU............* 00A0: 00000000 00000000 00000003 00000004 *................* 00B0: 00000000 00000000 00000000 00000000 *................* 00C0: 00000000 00000000 00000000 00000000 *................* 00D0: 00000000 00000000 00000000 00000000 *................* 00E0: 00000000 00000000 00000000 00000000 *................* 00F0: 00000000 00000000 00000000 00000700 *................* 0100: 00000001 * ....* ******************************** ENTRY 43 ******************************** Logging OS 2. Digital UNIX System Architecture 2. Alpha Event sequence number 6. Timestamp of occurrence 04-JUN-2001 17:11:13 Host name alpha System type register x00000016 Alpha 4000/1200 Series Number of CPUs (mpnum) x00000004 CPU logging event (mperr) x00000000 Event validity 1. O/S claims event is valid Event severity 5. Low Priority Entry type 100. CPU Machine Check Errors CPU Minor class 4. 620 System Correctable Error Software Flags x0000000000000000 Active CPUs x0000000F Hardware Rev x00000000 System Serial Number NI85113847 Module Serial Number Module Type x0000 System Revision x00000000 Machine Check Reason x0204 IOD Detected Soft Error Ext Interface Status Reg x0000000000000000 Register Contents Not Valid For This Error Ext Interface Address Reg x0000000000000000 Register Contents Not Valid For This Error Fill Syndrome Reg x0000000000000000 Register Contents Not Valid For This Error Interrupt Summary Reg x0000000000000000 Register Contents Not Valid For This Error WHOAMI x00000000 Register Contents Not Valid For This Error --IOD REGISTERS FOLLOW-- This Bus Bridge Phy Addr x000000FBE0000000 IOD# 1 Dev Type & Rev Register x06000332 CAP Chip Revision: x00000002 B3040 Revision: x00000003 B3050 Revision: x00000003 AlphaServer 4100 MC Error Info Register 0 x9B1840E0 MC Bus Trans Addr<31:4>: 9B1840E0 MC Error Info Register 1 x800FD600 MC bus trans addr <39:32> x00000000 MC Command is WriteBack Mem CPU3 OR IOD3 Master at Time of Error Device ID: x00000007 MC error info valid CAP Error Register x89000000 Error Detected but Not Logged Correctable ECC err det by MDPA MC error info latched MDPA Status Register x00000000 MDPA Status Register Data Not Valid MDPA Error Syndrome Reg x00000000 MDPA Syndrome Register Data Not Valid MDPB Status Register x00000000 MDPB Status Register Data Not Valid MDPB Error Syndrome Reg x00000000 MDPB Syndrome Register Data Not Valid PALcode Revision Palcode Rev: 1.21-26 ******************************** ENTRY 44 ******************************** Logging OS 2. Digital UNIX System Architecture 2. Alpha Event sequence number 5. Timestamp of occurrence 04-JUN-2001 17:11:13 Host name alpha System type register x00000016 Alpha 4000/1200 Series Number of CPUs (mpnum) x00000004 CPU logging event (mperr) x00000000 Event validity 1. O/S claims event is valid Event severity 5. Low Priority Entry type 100. CPU Machine Check Errors CPU Minor class 4. 620 System Correctable Error Software Flags x0000000000000000 Active CPUs x0000000F Hardware Rev x00000000 System Serial Number NI85113847 Module Serial Number Module Type x0000 System Revision x00000000 Machine Check Reason x0204 IOD Detected Soft Error Ext Interface Status Reg x0000000000000000 Register Contents Not Valid For This Error Ext Interface Address Reg x0000000000000000 Register Contents Not Valid For This Error Fill Syndrome Reg x0000000000000000 Register Contents Not Valid For This Error Interrupt Summary Reg x0000000000000000 Register Contents Not Valid For This Error WHOAMI x00000000 Register Contents Not Valid For This Error --IOD REGISTERS FOLLOW-- This Bus Bridge Phy Addr x000000F9E0000000 IOD# 0 Dev Type & Rev Register x06008332 CAP Chip Revision: x00000002 B3040 Revision: x00000003 B3050 Revision: x00000003 AlphaServer 4100 MC Error Info Register 0 x9B1840E0 MC Bus Trans Addr<31:4>: 9B1840E0 MC Error Info Register 1 x800FD600 MC bus trans addr <39:32> x00000000 MC Command is WriteBack Mem CPU3 OR IOD3 Master at Time of Error Device ID: x00000007 MC error info valid CAP Error Register x89000000 Error Detected but Not Logged Correctable ECC err det by MDPA MC error info latched MDPA Status Register x00000000 MDPA Status Register Data Not Valid MDPA Error Syndrome Reg x00000000 MDPA Syndrome Register Data Not Valid MDPB Status Register x00000000 MDPB Status Register Data Not Valid MDPB Error Syndrome Reg x00000000 MDPB Syndrome Register Data Not Valid PALcode Revision Palcode Rev: 1.21-26 ******************************** ENTRY 45 ******************************** Logging OS 2. Digital UNIX System Architecture 2. Alpha Event sequence number 4. Timestamp of occurrence 04-JUN-2001 17:10:47 Host name alpha System type register x00000016 Alpha 4000/1200 Series Number of CPUs (mpnum) x00000004 CPU logging event (mperr) x00000000 Event validity 1. O/S claims event is valid Event severity 5. Low Priority Entry type 100. CPU Machine Check Errors CPU Minor class 4. 620 System Correctable Error Software Flags x0000000000000000 Active CPUs x0000000F Hardware Rev x00000000 System Serial Number NI85113847 Module Serial Number Module Type x0000 System Revision x00000000 Machine Check Reason x0204 IOD Detected Soft Error Ext Interface Status Reg x0000000000000000 Register Contents Not Valid For This Error Ext Interface Address Reg x0000000000000000 Register Contents Not Valid For This Error Fill Syndrome Reg x0000000000000000 Register Contents Not Valid For This Error Interrupt Summary Reg x0000000000000000 Register Contents Not Valid For This Error WHOAMI x00000000 Register Contents Not Valid For This Error --IOD REGISTERS FOLLOW-- This Bus Bridge Phy Addr x000000FBE0000000 IOD# 1 Dev Type & Rev Register x06000332 CAP Chip Revision: x00000002 B3040 Revision: x00000003 B3050 Revision: x00000003 AlphaServer 4100 MC Error Info Register 0 xA19840E0 MC Bus Trans Addr<31:4>: A19840E0 MC Error Info Register 1 x801ECA00 MC bus trans addr <39:32> x00000000 MC Command is ReadMod0-Mem Device ID: x00000003 MC bus error assoc w read/dirty MC error info valid CAP Error Register x88000000 Correctable ECC err det by MDPA MC error info latched MDPA Status Register x00000000 MDPA Status Register Data Not Valid MDPA Error Syndrome Reg x00000000 MDPA Syndrome Register Data Not Valid MDPB Status Register x00000000 MDPB Status Register Data Not Valid MDPB Error Syndrome Reg x00000000 MDPB Syndrome Register Data Not Valid PALcode Revision Palcode Rev: 1.21-26 ******************************** ENTRY 46 ******************************** Logging OS 2. Digital UNIX System Architecture 2. Alpha Event sequence number 3. Timestamp of occurrence 04-JUN-2001 17:10:47 Host name alpha System type register x00000016 Alpha 4000/1200 Series Number of CPUs (mpnum) x00000004 CPU logging event (mperr) x00000000 Event validity 1. O/S claims event is valid Event severity 5. Low Priority Entry type 100. CPU Machine Check Errors CPU Minor class 4. 620 System Correctable Error Software Flags x0000000000000000 Active CPUs x0000000F Hardware Rev x00000000 System Serial Number NI85113847 Module Serial Number Module Type x0000 System Revision x00000000 Machine Check Reason x0204 IOD Detected Soft Error Ext Interface Status Reg x0000000000000000 Register Contents Not Valid For This Error Ext Interface Address Reg x0000000000000000 Register Contents Not Valid For This Error Fill Syndrome Reg x0000000000000000 Register Contents Not Valid For This Error Interrupt Summary Reg x0000000000000000 Register Contents Not Valid For This Error WHOAMI x00000000 Register Contents Not Valid For This Error --IOD REGISTERS FOLLOW-- This Bus Bridge Phy Addr x000000F9E0000000 IOD# 0 Dev Type & Rev Register x06008332 CAP Chip Revision: x00000002 B3040 Revision: x00000003 B3050 Revision: x00000003 AlphaServer 4100 MC Error Info Register 0 xA19840E0 MC Bus Trans Addr<31:4>: A19840E0 MC Error Info Register 1 x801ECA00 MC bus trans addr <39:32> x00000000 MC Command is ReadMod0-Mem Device ID: x00000003 MC bus error assoc w read/dirty MC error info valid CAP Error Register x88000000 Correctable ECC err det by MDPA MC error info latched MDPA Status Register x00000000 MDPA Status Register Data Not Valid MDPA Error Syndrome Reg x00000000 MDPA Syndrome Register Data Not Valid MDPB Status Register x00000000 MDPB Status Register Data Not Valid MDPB Error Syndrome Reg x00000000 MDPB Syndrome Register Data Not Valid PALcode Revision Palcode Rev: 1.21-26 ******************************** ENTRY 47 ******************************** Logging OS 2. Digital UNIX System Architecture 2. Alpha Event sequence number 2. Timestamp of occurrence 04-JUN-2001 17:10:47 Host name alpha System type register x00000016 Alpha 4000/1200 Series Number of CPUs (mpnum) x00000004 CPU logging event (mperr) x00000001 Event validity 1. O/S claims event is valid Event severity 5. Low Priority Entry type 100. CPU Machine Check Errors CPU Minor class 4. 620 System Correctable Error Software Flags x0000000000000000 Active CPUs x0000000F Hardware Rev x00000000 System Serial Number NI85113847 Module Serial Number Module Type x0000 System Revision x00000000 Machine Check Reason x0086 Alpha Chip Detected ECC Error, From Memory Ext Interface Status Reg xFFFFFFF0C5FFFFFF DATA SOURCE IS MEMORY OR SYSTEM CORRECTABLE ECC ERROR D-ref fill EV5 Chip Rev 5 Ext Interface Address Reg xFFFFFF00A19840FF Fill Syndrome Reg x0000000000000029 Interrupt Summary Reg x0000000100000000 Correctable ECC Errors (IPL31) AST Requests 3-0: x0000000000000000 WHOAMI x00000001 CPU1 Detected This Error --IOD REGISTERS FOLLOW-- Base Addr of Bridge x0000000000000000 Register Contents Not Valid For This Error Dev Type & Rev Register x00000000 Register Contents Not Valid For This Error MC Error Info Register 0 x00000000 Register Contents Not Valid For This Error MC Error Info Register 1 x00000000 Register Contents Not Valid For This Error CAP Error Register x00000000 Register Contents Not Valid For This Error MDPA Status Register x00000000 MDPA Status Register Data Not Valid MDPA Error Syndrome Reg x00000000 MDPA Syndrome Register Data Not Valid MDPB Status Register x00000000 MDPB Status Register Data Not Valid MDPB Error Syndrome Reg x00000000 MDPB Syndrome Register Data Not Valid PALcode Revision Palcode Rev: 1.21-27