Jane C. Blake,
Managing Editor

This issue of the Digital Technical Journal contains a collection of papers on two general topics - VAXcluster systems, and network adapters and performance. The first set of three papers describes new VMS VAXcluster developments and features; the second set addresses the topics of LAN adapter design and performance measurement techniques. A common theme across these papers is the development of technologies for interconnecting systems that offer high data availability without sacrificing performance.

VMS Volume shadowing, described by Scott Davis, is a means of ensuring data availability and integrity in VMS VAZcluster systems. By maintaining multiple copies of data on separate devices, the volume shadowing technique prevents data from being lost as the result of media deterioration or device failures. Scott discusses the advantage of the new design over controller-based shadowing and explains how this fully distributed software makes a broad range of topologies suitable for shadowing.

The growth capabilities and availability of VMS VAXcluster systems are characteristics well suited to applications with high-availability requirements. Sandy Shaman first prevents an overview of the VAXcluster system architecture, including explanations of the layers, their purpose and function. He then gives practical insights into how the system implementation affects application design and reviews the choices available to application designers in the area of client-server computing and data sharing.

The availability of applications and cluster configurations is also enhanced by developments in a new release of the VMS operating system. Lee Leahy describes a VMS feature that enable fail-over between multiple LAN adapters and compares this approach to a single-adapter implementation. He then discusses and give examples of VMS features for network delay detection and reduction, and failure analysis in local area VAXcluster systems.

The focus then moves from VMS-level concerns to the design of network adapters and performance measurement. The adapter described by Dick Stockdale and Judy Weiss is the DEC LANcontroller 400, which connects systems based on Digital's XMI bus to an Ethernet LAN. This particular design improves on previous designs by transforming the adapter from a dumb to an intelligent adapter which can off-load the host. Consequently, the adapter supports systems that utilize the full bandwidth of Ethernet. The authors provide a system overview, performance metrics, and a critical examination of firmware-based design.

Like the LANcontroller 400. the FDDI controller 400 is an adapter that interfaces XMI-based systems to a LAN. However, as Satish Rege relates, this adapter was required to transmit data 30 times faster than Ethernet adapters. Satish discusses the architecture and examines the choices the designers made to address the problem of interfacing a parallel high-bandwidth CPU bus (XMI) to a serial fiber-optic network bus (FDDI). Their design choices include a three-stage pipeline approach to buffering that enables these stages to proceed in an asynchronous fashion.

To ensure that the performance goals for the FDDIcontroller would be met, a simulation model was created. In his paper about the model, Ram Kalkunte details the modeling methodology, reviews model components, and presents simulation results. Ram describes how in addition to performance projections, the model provided designers with buffer sufficiency analysis and helped engineers analyze the functional correctness of the adapter design.

The high level of performance achieved by the FDDI controller was driven by the high performance of the FDDI LAN itself - 100 megabits per second. Ray Jain's subject is performance measurement at the level of the FDDI LAN. Raj describes the performance analysis of Digital's implementation of FDDI and how various parameters affect system performance. As part of his presentation of the modeling and simulation methods used, he shared guidelines for setting the value of one of the key parameters, target token rotation time, to optimize performance. Raj has recently published a book on computer systems performance analysis, which is reviewed in the Further Readings section of this issue.