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When displaying an ASCII string value, the debugger encloses it within quotation marks (") or apostrophes ('), depending on the language syntax. For example:
DBG> EXAMINE EMPLOYEE_NAME PAYROLL\EMPLOYEE_NAME: "Peter C. Lombardi" DBG> |
To deposit a string value (including a single character) into a string variable, you must enclose the value in quotation marks (") or apostrophes ('). For example:
DBG> DEPOSIT PART_NUMBER = "WG-7619.3-84" DBG> |
If the string has more ASCII characters (1 byte each) than can fit into the location denoted by the address expression, the debugger truncates the extra characters from the right and issues the following message:
%DEBUG-I-ISTRTRU, string truncated at or near DEPOSIT |
If the string has fewer characters, the debugger pads the remaining
characters to the right of the string by inserting ASCII space
characters.
4.2.3 Array Types
You can examine an entire array aggregate, a single indexed element, or a slice (a range of elements). However, you can deposit into only one element at a time. The following examples show typical operations with arrays.
The following command displays the values of all the elements of the array variable ARRX, a one-dimensional array of integers:
DBG> EXAMINE ARRX
MOD3\ARRX
(1): 42
(2): 17
(3): 278
(4): 56
(5): 113
(6): 149
DBG>
|
The following command displays the value of element 4 of array ARRX (depending on the language, parentheses or brackets are used to denote indexed elements):
DBG> EXAMINE ARRX(4) MOD3\ARRX(4): 56 DBG> |
The following command displays the values of all the elements in a slice of ARRX. This slice consists of the range of elements from element 2 to element 5:
DBG> EXAMINE ARRX(2:5)
MOD3\ARRX
(2): 17
(3): 278
(4): 56
(5): 113
DBG>
|
In general, a range of values to be examined is denoted by two values separated by a colon (value1:value2). Depending on the language, two periods (..) can be used instead of a colon.
You can deposit a value to only a single array element at a time (you cannot deposit to an array slice or an entire array aggregate with a single DEPOSIT command). For example, the following command deposits the value 53 into element 2 of ARRX:
DBG> DEPOSIT ARRX(2) = 53 DBG> |
The following command displays the values of all the elements of array REAL_ARRAY, a two-dimensional array of real numbers (three per dimension):
DBG> EXAMINE REAL_ARRAY PROG2\REAL_ARRAY (1,1): 27.01000 (1,2): 31.00000 (1,3): 12.48000 (2,1): 15.08000 (2,2): 22.30000 (2,3): 18.73000 DBG> |
The debugger issues a diagnostic message if you try to deposit to an index value that is out of bounds. For example:
DBG> DEPOSIT REAL_ARRAY(1,4) = 26.13 %DEBUG-I-SUBOUTBND, subscript 2 is out of bounds, value is 4, bounds are 1..3 DBG> |
In the previous example, the deposit operation was executed because the diagnostic message is of I level. This means that the value of some array element adjacent to (1,3), possibly (2,1) might have been affected by the out-of-bounds deposit operation.
To deposit the same value to several components of an array, you can use a looping command such as FOR or REPEAT. For example, assign the value RED to elements 1 to 4 of the array COLOR_ARRAY:
DBG> FOR I = 1 TO 4 DO (DEPOSIT COLOR_ARRAY(I) = RED) DBG> |
You can also use the built-in symbols (.) and (^) to step through array
elements, as explained in Section 4.1.8.
4.2.4 Record Types
The generic term record is used here to denote a data structure whose elements have heterogeneous data types---what is called a struct type in the C language. |
You can examine an entire record aggregate, a single record component, or several components. However, you can deposit into only one component at a time. The following examples show typical operations with records.
The following command displays the values of all the components of the record variable PART:
DBG> EXAMINE PART
INVENTORY\PART:
ITEM: "WF-1247"
PRICE: 49.95
IN_STOCK: 24
DBG>
|
The following command displays the value of component IN_STOCK of record PART (general syntax):
DBG> EXAMINE PART.IN_STOCK INVENTORY\PART.IN_STOCK: 24 DBG> |
The following command displays the value of the same record component using COBOL syntax (the language must be set to COBOL):
DBG> EXAMINE IN_STOCK OF PART
INVENTORY\IN_STOCK of PART:
IN_STOCK: 24
DBG>
|
The following command displays the values of two components of record PART:
DBG> EXAMINE PART.ITEM, PART.IN_STOCK INVENTORY\PART.ITEM: "WF-1247" INVENTORY\PART.IN_STOCK: 24 DBG> |
The following command deposits a value into record component IN_STOCK:
DBG> DEPOSIT PART.IN_STOCK = 17 DBG> |
You can examine the entity designated (pointed to) by a pointer variable and deposit a value into that entity. You can also examine a pointer variable.
For example, the following Pascal code declares a pointer variable A that designates a value of type real:
.
.
.
TYPE
T = ^REAL;
VAR
A : T;
.
.
.
|
The following command displays the value of the entity designated by the pointer variable A:
DBG> EXAMINE A^ MOD3\A^: 1.7 DBG> |
In the following example, the value 3.9 is deposited into the entity designated by A:
DBG> DEPOSIT A^ = 3.9 DBG> EXAMINE A^ MOD3\A^: 3.9 DBG> |
When you specify the name of a pointer variable with the EXAMINE command, the debugger displays the memory address of the object it designates. For example:
DBG> EXAMINE/HEXADECIMAL A SAMPLE\A: 0000B2A4 DBG> |
The debugger recognizes address expressions that are associated with instructions. This enables you to examine and deposit instructions using the same basic techniques as with variables.
When debugging at the instruction level, you might find it convenient to first enter the following command. It sets the default step mode to stepping by instruction:
DBG> SET STEP INSTRUCTION DBG> |
There are other step modes that enable you to execute the program to specific kinds of instructions. You can also set breakpoints to interrupt execution at these instructions.
In addition, you can use a screen-mode instruction display (see
Section 7.4.4) to display the actual decoded instruction stream of your
program.
4.3.1 Examining Instructions
If you specify an address expression that is associated with an instruction in an EXAMINE command (for example, a line number), the debugger displays the first instruction at that location. You can then use the period (.), Return key, and circumflex (^) to display the current, next, and previous instruction (logical entity), as described in Section 4.1.8.
For example, on Alpha processors:
DBG> EXAMINE %LINE 12 MOD3\%LINE 12: BIS R31,R31,R2 DBG> EXAMINE MOD3\%LINE 12+4: BIS R31,R2,R0 ! Next instruction DBG> EXAMINE MOD3\%LINE 12+8: ADDL R31,R0,R0 ! Next instruction DBG> EXAMINE ^ MOD3\%LINE 12+4: BIS R31,R2,R0 ! Previous instruction DBG> |
Line numbers, routine names, and labels are symbolic address expressions that are associated with instructions. In addition, instructions might be stored in various other memory addresses and in certain registers during the execution of your program.
The program counter (PC) is the register that contains the address of the next instruction to be executed by your program. The command EXAMINE .%PC displays that instruction. The period (.), when used directly in front of an address expression, denotes the contents of operator---that is, the contents of the location designated by the address expression. Note the following distinction:
As shown in the previous examples, the debugger knows whether an address expression is associated with an instruction. If it is, the EXAMINE command displays that instruction (you do not need to use the /INSTRUCTION qualifier). You use the /INSTRUCTION qualifier to display the contents of an arbitrary program location as an instruction---that is, the command EXAMINE/INSTRUCTION causes the debugger to interpret and format the contents of any program location as an instruction (see Section 4.5.2).
When you examine consecutive instructions in a MACRO-32 program, the debugger might misinterpret data as instructions if storage for the data is allocated in the middle of a stream of instructions. The following example shows this problem. It shows some MACRO-32 code with two longwords of data storage allocated directly after the BRB instruction at line 7 (line numbers have been added to the example for clarity).
module TEST
1: .TITLE TEST
2:
3: TEST$START::
4: .WORD 0
5:
6: MOVL #2,R2
7: BRB LABEL_2
8:
9: .LONG ^X12345
10: .LONG ^X14465
11:
12: LABEL_2:
13: MOVL #5,R5
14:
15: .END TEST$START
|
The following EXAMINE command displays the instruction at the start of line 6:
DBG> EXAMINE %LINE 6 TEST\TEST$START\%LINE 6: MOVL S^#02,R2 DBG> |
The following EXAMINE command correctly interprets and displays the logical successor entity as an instruction at line 7:
DBG> EXAMINE TEST\TEST$START\%LINE 7: BRB TEST\TEST$START\LABEL_2 DBG> |
However, the following three EXAMINE commands incorrectly interpret the three logical successors as instructions:
DBG> EXAMINE TEST\TEST$START\%LINE 7+2: MULF3 S^#11.00000,S^#0.5625000,S^#0.5000000 DBG> EXAMINE %DEBUG-W-ADDRESSMODE, instruction uses illegal or undefined addressing modes TEST\TEST$START\%LINE 7+6: MULD3 S^#0.5625000[R4],S^#0.5000000,@W^5505(R0) DBG> EXAMINE TEST$START+12: HALT DBG> |
The EXAMINE command displays contents of any register that is
accessible in your program. You can use the DEPOSIT command to change
the contents of these registers. The number and type of registers vary
for each OpenVMS platform, as described in the following sections.
4.4.1 Examing and Depositing into Alpha Registers
On Alpha processors, the Alpha architecture provides 32 general (integer) registers and 32 floating-point registers, some of which are used for temporary address and data storage. Table 4-1 identifies the debugger built-in symbols that refer to Alpha registers.
| Symbol | Description |
|---|---|
| Alpha Integer Registers | |
| %R0...%R28 | Registers R0...R28 |
| %FP (%R29) | Stack frame base register (FP) |
| %SP (%R30) | Stack pointer (SP) |
| %R31 | ReadAsZero/Sink (RZ) |
| %PC | Program counter (PC) |
| %PS | Processor status register (PS). The built-in symbols %PSL and %PSW are disabled for Alpha processors. |
| Alpha Floating-Point Registers | |
| %F0...%F30 | Registers F0...F30 |
| %F31 | ReadAsZero/Sink |
On Alpha processors:
The following examples show how to examine and deposit into registers:
DBG> SHOW TYPE ! Show type for locations without type: long integer ! a compiler-generated type. DBG> SHOW RADIX ! Identify current radix. input radix: decimal output radix: decimal DBG> EXAMINE %R11 ! Display value in R11. MOD3\%R11: 1024 DBG> DEPOSIT %R11 = 444 ! Deposit new value into R11. DBG> EXAMINE %R11 ! Check new value. R11: 444 DBG> EXAMINE %PC ! Display value in program counter. MOD\%PC: 1553 DBG> EXAMINE %SP ! Display value in stack pointer. 0\%SP: 2147278720 DBG> |
See Section 4.3.1 for specific information about the PC.
On Alpha processors, the processor status (PS) is a register whose value represents a number of processor state variables. The first three bits of the PS are reserved for the use of the software. The values of these bits can be controlled by a user program. The remainder of the bits, bits 4 to 64, contain privileged information and cannot be altered by a user-mode program.
The following example shows how to examine the contents of the PS:
DBG> EXAMINE %PS
MOD1\%PS:
SP_ALIGN IPL VMM CM IP SW
48 0 0 USER 0 3
DBG>
|
See the Alpha Architecture Reference Manual for complete information about the PS, including the values of the various bits.
You can also display the information in the PS in other formats. For example:
DBG> EXAMINE/LONG/HEX %PS MOD1\%PS: 0000001B DBG> EXAMINE/LONG/BIN %PS MOD1\%PS: 00000000 00000000 00000000 00011011 DBG> |
The command EXAMINE/PS displays the value at any location in PS format.
This is useful for examining the combined current and saved PS values.
4.4.2 Examing and Depositing into Integrity server Registers
On Integrity server processors, the Integrity server architecture provides:
Most of these registers are read/writable from user mode debug. Some, however, are not writable and others are only accessible from the higher privileges related with the System Code Debugger (SCD) configuration (see OpenVMS Alpha System Analysis Tools Manual).
| Symbol | Description |
|---|---|
| Integrity server Application Registers | |
| %KR0...%KR7 | Kernel registers 0...7 |
| %RSC (%AR16) | Register Stack Configuration |
| %BSP (%AR17) | Backing Store Pointer |
| %BSPSTORE (%AR18) | Backing Store Pointer for Memory Stores |
| %RNAT (%AR19) | RSE NaT Collection |
| %CCV ($AR32) | Compare and Exchange Compare Value |
| %UNAT (%AR36) | User NaT Collection |
| %FPSR (%AR40) | Floating-point Status |
| %PFS (%AR64) | Previous Function State |
| %LC (%AR65) | Loop Count |
| %EC (%AR66) | Epilog Count |
| %CSD | Code Segment |
| %SSD | Stack Segment |
| Control Registers | |
| %DCR (%CR0) | Default Control |
| %ITM (%CR1) | Interval Timer Match (only visible for SCD) |
| %IVA (%CR2) | Interruption Vector Address (only visible for SCD) |
| %PTA (%CR8) | Page Table Address (only visible for SCD) |
| %PSR (%CR9, %ISPR) | Interruption Processor Status |
| %ISR (%CR17) | Interruption Status |
| %IIP (%CR19) | Interruption Instruction Pointer |
| %IFA (%CR20) | Interruption Faulting Address |
| %ITIR (%CR21) | Interruption TLB Insertion |
| %IIPA (%CR22) | Interruption Instruction Previous |
| %IFS (%CR23) | Interruption Function State |
| %IIM (%CR24) | Interruption Immediate |
| %IHA (%CR25) | Interruption Hash Address |
| %LID (%CR64) | Local Interrupt ID (only visible for SCD) |
| %TPR (%CR66) | Task Priority (only visible for SCD) |
| %IRR0...%IRR3 (%CR68...%CR71) | External Interrupt Request 0...3 (only visible for SCD) |
| %ITV (%CR72) | Interval Timer (only visible for SCD) |
| %PMV (%CR73) | Performance Monitoring (only visible for SCD) |
| %CMCV (%CR74) | Corrected Machine Check Vector (only visible for SCD) |
| %IRR0 and %IRR1 (%CR80 and %CR81) | Local Redirection 0:1 (only visible for SCD) |
| Special Registers | |
| %IH (%SR0) | Invocation Handle |
| %PREV_BSP | Previous Backing Store Pointer |
| %PC (%IP) | Program Counter (Instruction Pointer | slot number) |
| %RETURN_PC | Return Program Counter |
| %CFM | Current Frame Marker |
| %NEXT_PFS | Next Previous Frame State |
| %PSP | Previous Stack Pointer |
| %CHFCTX_ADDR | Condition Handling Facility Context Address |
| %OSSD | Operating System Specific Data |
| %HANDLER_FV | Handler Function Value |
| %LSDA | Language Specific Data Area |
| %UM | User Mask |
| Predicate Registers | |
| %PR (%PRED) | Predicate Collection Register---Collection of %P0...%P63 |
| %P0...%P63 | Predicate (single-bit)Registers 0...63 |
| Branch Registers | |
| %RP (%B0) | Return Pointer |
| %B1...%B7 | Branch Registers 1...7 |
| General Integer Registers | |
| %R0 | General Integer Register 0 |
| %GP (%R1) | Global Data Pointer |
| %R2...%R11 | General Integer Registers 2...11 |
| %SP (%R12) | Stack Pointer |
| %TP (%R13) | Thread Pointer |
| %R14...%R24 | General Integer Registers 14...24 |
| %AP (%R25) | Argument Information |
| %R26...%R127 | General Integer Registers 26...127 |
| Output Registers | |
| %OUT0...%OUT7 | Output Registers, runtime aliases (i.e., If the frame has allocated output registers, then %OUT0 maps to the first allocated output registers, for example, %R38, etc.) |
| General Registers | |
| %GRNAT0 and %GRNAT1 | General Register Not A Thing (NAT) collection registers 64 bits each, for example, %GRNAT0<3,1,0> is the NAT bit for %R3. |
| Floating Point Registers | |
| %F0...%F127 | Floating Point Registers 0...127 |
On Integrity server processors:
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