Table 3-2 Removed Routines
| Removed Routine |
Replacement |
Comments |
|
MMG$ALCSTX
|
MMG_STD$ALCSTX
|
Returns new-style section index.
|
|
MMG$ALLOC_PFN_ALGND
|
MMG$ALLOC_PFN_ALGND_64
|
MMG$ALLOC_PFN_ALGND_64 should not be called directly. Instead, use the
ALLOCPFN macro. Note that 64-bit virtual addresses are required to
access PFN database entries.
|
|
MMG$ALLOC_ZERO_ALGND
|
MMG$ALLOC_ZERO_ALGND_64
|
MMG$ALLOC_ZERO_ALGND_64 should not be called directly. Instead, use the
ALLOC_ZERO_PFN macro. Note that 64-bit virtual addresses are required
to access PFN database entries.
|
|
MMG$CREPAG
|
MMG$CREPAG_64
MMG_STD$CREPAG_64
|
Accepts 64-bit addresses and has 3 new inputs: RDE (R12),
pagefile_cache (R13) mmg_flags (R14). See mmg_routines.h for STD
interface.
|
|
MMG$DALCSTX
|
MMG_STD$DALCSTX
|
Accepts new-style section index.
|
|
MMG$DECPTREF
|
MMG_STD$DECPTREF_PFNDB
MMG_STD$DECPTREF_GPT
|
MMG$DECPTREF expected a 32-bit system space address of a PTE as an
input parameter. Page table entries are now located in 64-bit
addressable memory. This routine was replaced by two routines:
MMG_STD$DECPTREF_PFNDB and MMG_STD$DECPTREF_GPT.
MMG_STD$DECPTREF_PFNDB accepts as input a 64-bit virtual address of
a PFN database entry for a page table, the reference count of which is
to be decremented.
MMG_STD$DECPTREF_GPT, accepts as input a 64-bit virtual address of
a global page table entry, which lies within a certain global page
table page, of which a reference count must be decremented.
|
|
MMG$DECSECREF
|
MMG_STD$DECSECREF
|
Accepts new-style section index.
|
|
MMG$DECSECREFL
|
MMG_STD$DECSECREFL
|
Accepts new-style section index.
|
|
MMG$DELPAG
|
MMG$DELPAG_64
MMG_STD$DELPAG_64
|
Accepts 64-bit addresses and has 2 new inputs, RDE (R12) and mmg_flags
(R14). See mmg_routines.h for STD interface.
|
|
MMG$DELWSLEPPG
|
MMG_STD$DELWSLEPPG_64
|
Replacement reflects a change in input from a 32-bit addressable system
space address of a PTE to a 64-bit address of a PTE in page table
space. Other argument changes may have occurred as well.
|
|
MMG$DELWSLEX
|
MMG_STD$DELWSLEX_64
|
Replacement reflects a change in input from a 32-bit addressable system
space address of a PTE to a 64-bit address of a PTE in page table
space. Other argument changes may have occurred as well.
|
|
MMG$FREWSLX
|
MMG$FREWSLX_64
|
Replacement reflects a change in input from a 32-bit addressable system
space address of a PTE to a 64-bit address of a PTE in page table
space. Other argument changes may have occurred as well.
|
|
MMG$GETGSNAM
|
MMG_STD$GETGSNAM
|
Converted to STD interface. (No prototype in mmg_routines.h.)
|
|
MMG$GSDSCAN
|
MMG_STD$GSDSCAN
|
Converted to STD interface. See mmg_routines.h for interface definition.
|
|
MMG$INCPTREF
|
MMG_STD$INCPTREF_64
|
Replacement reflects a change in input from a 32-bit addressable system
space address of a PTE to a 64-bit address of a PTE in page table
space. Other argument changes may have occurred as well.
|
|
MMG$INIBLDPKT
|
None
|
This routine was used internally only. Its symbol has been removed from
the base image.
|
|
MMG$ININEW_PFN
|
MMG_STD$ININEWPFN_64
|
Replacement reflects a change in input from a 32-bit addressable system
space address of a PTE to a 64-bit address of a PTE in page table
space. Other argument changes may have occurred as well.
|
|
MMG$INIT_PGFLQUOTA
|
MMG_STD$INIT_PGFLQUOTA
$INIT_PGFLQUOTA
|
Converted to STD interface. See mmg_functions.h for interface
definition.
|
|
MMG$IN_REGION
|
MMG_STD$IN_REGION_64
$IN_REGION_64
|
Converted to STD interface. See mmg_functions.h for interface
definition.
|
|
MMG$IOLOCK
|
MMG_STD$IOLOCK_BUF
|
See Appendix B.
|
|
MMG$LOCKPGTB
|
MMG_STD$LOCKPGTB_64
|
Replacement reflects a change in input from a 32-bit addressable system
space address of a PTE to a 64-bit address of a PTE in page table
space. Other argument changes may have occurred as well.
|
|
MMG$MAKE_WSLE
|
MMG_STD$MAKE_WSLE_64
|
Replacement reflects a change in input from a 32-bit addressable system
space address of a PTE to a 64-bit address of a PTE in page table
space. Other argument changes may have occurred as well.
|
|
MMG$MORE_PGFLQUOTA
|
MMG_STD$MORE_PGFLQUOTA
$MORE_PGFLQUOTA
|
Converted to STD interface. See mmg_functions.h for interface
definition.
|
MMG$MOVPTLOCK
MMG$MOVPTLOCK1
|
None
|
Page table locking redesign has obviated these routines. No replacement
exists.
|
|
MMG$PTEINDX
|
None
|
Used internally only. Obviated by design as of Version 7.0.
|
|
MMG$PTEREF
|
MMG$PTEREF_64
|
This replacement reflects a change in interface including
MMG_STD$PTEREF acceptance as input a 64-bit virtual address.
|
|
MMG$PURGEMPL
|
MMG$PURGE_MPL
|
Renamed because the interface changed slightly. This is a JSB entry
with arguments in R0-R2. It now accepts an additional argument in R3,
the PTBR of the process owning the PTEs, for range-based requests. This
request type also now accepts 64-bit PTE addresses rather than 32-bit
SVAPTE addresses.
|
|
MMG$SUBSECREF
|
MMG_STD$DECSECREFL
|
Accepts new-style section index.
|
|
MMG$SUBSECREFL
|
MMG_STD$SUBSECREFL
|
Accepts new-style section index.
|
|
MMG$TBI_SINGLE_64
|
TBI_SINGLE Macro
|
MMG$TBI_SINGLE_64 should not be called directly. Instead, use the
TBI_SINGLE macro.
|
|
MMG$TRY_ALL
|
MMG_STD$TRY_ALL_64
|
Converted to STD interface. See mmg_routines.h for interface definition.
|
|
MMG$ULKGBLWSL
|
None
|
This routine was used internally only. Its symbol has been removed from
the base image.
|
|
MMG$UNLOCK
|
MMG_STD$IOUNLOCK_BUF
|
See Appendix B.
|
|
MMG_STD$ALLOC_PFN
|
MMG_STD$ALLOC_PFN_64
|
This routine should not be called directly. Instead, use the ALLOCPFN
macro. Note that 64-bit virtual addresses are required to access PFN
database entries.
|
|
MMG_STD$ALLOC_ZERO_PFN
|
MMG_STD$ALLOC_ZERO_PFN_64
|
This routine should not be called directly. Instead, use the
ALLOC_ZERO_PFN macro. Note that 64-bit virtual addresses are required
to access PFN database entries.
|
|
MMG_STD$DALLOC_PFN
|
MMG_STD$DALLOC_PFN_64
|
Note that 64-bit virtual addresses are required to access PFN database
entries.
|
|
MMG_STD$DEL_PFNLST
|
MMG_STD$DEL_PFNLST_64
|
Note that 64-bit virtual addresses are required to access PFN database
entries.
|
|
MMG_STD$ININEW_PFN
|
MMG_STD$ININEWPFN_64
|
Note that 64-bit virtual addresses are required to access PFN database
entries.
|
|
MMG_STD$INS_PFNH
|
MMG_STD$INS_PFNH_64
|
Note that the 64-bit virtual addresses are required to access PFN
database entries.
|
|
MMG_STD$INS_PFNT
|
MMG_STD$INS_PFNT_64
|
Note that the 64-bit virtual addresses are required to access PFN
database entries.
|
|
MMG_STD$IOLOCK
|
MMG_STD$IOLOCK_BUF
|
See Appendix B.
|
|
MMG_STD$PTEINDX
|
None
|
Used internally only. Obviated by design as of OpenVMS Alpha Version
7.0.
|
|
MMG_STD$REL_PFN
|
MMG_STD$REL_PFN_64
|
Note that the 64-bit virtual addresses are required to access PFN
database entries.
|
|
MMG_STD$REM_PFN
|
MMG_STD$REM_PFN_64
|
Note that the 64-bit virtual addresses are required to access PFN
database entries.
|
|
MMG_STD$REM_PFNH
|
MMG_STD$REM_PFNH_64
|
Note that the 64-bit virtual addresses are required to access PFN
database entries.
|
|
MMG_STD$TBI_SINGLE_64
|
TBI_SINGLE Macro
|
MMG_STD$TBI_SINGLE_64 should not be called directly. Instead, use the
TBI_SINGLE macro.
|
|
MMG_STD$UNLOCK
|
MMG_STD$IOUNLOCK_BUF
|
See Appendix B.
|
|
SWP$FILL_L1L2_PT
|
None
|
Removed.
|
Table 3-3 Removed System Data Cells
| Removed Cell |
Replacement |
Comments |
|
CTL$AL_STACK
|
CTL$AQ_STACK
|
Arrays are now quadwords.
|
|
|
|
|
|
CTL$AL_STACKLIM
|
CTL$AQ_STACKLIM
|
Arrays are now quadwords.
|
|
|
|
|
|
EXE$GL_GPT
|
MMG$GQ_FREE_GPT
|
As of Version 7.0, free GPTEs are managed in the same manner as free
system PTEs. Note that 64-bit virtual addresses are required to access
GPTEs.
|
|
|
|
|
|
LDR$GL_FREE_PT
|
LDR$GQ_FREE_S0S1_PT
|
Contains the address of the start of the free S0/S1 PTE list. The
format of the free PTEs has changed for Version 7.0.
|
|
|
|
|
|
MMG$GL_FRESVA
|
MMG$GQ_NEXT_FREE_S0S1_VA
|
|
|
|
|
|
|
MMG$GL_GPTBASE
|
MMG$GQ_GPT_BASE
|
As of Version 7.0, free GPTEs are managed in the same manner as free
system PTEs. Note that 64-bit virtual addresses are required to access
GPTEs.
|
|
|
|
|
|
MMG$GL_MAXGPTE
|
MMG$GQ_MAX_GPTE
|
As of Version 7.0, free GPTEs are managed in the same manner as free
system PTEs. Note that 64-bit virtual addresses are required to access
GPTEs.
|
|
|
|
|
|
MMG$GL_P0_PTLEN
|
None
|
Obviated by the removal of the process page tables from the balance
slot.
|
|
|
|
|
|
MMG$GL_PX_VPN_LENGTH
|
None
|
This data cell is obviated by the removal of the process page tables
from the balance slot.
|
|
|
|
|
|
MMG$GL_RESERVED_SVA
|
MMG$GQ_WINDOW_VA
|
Increased in length to quadword.
|
|
|
|
|
|
MMG$GL_RESERVED_SVA2
|
MMG$GQ_WINDOW2_VA
|
Increased in length to quadword.
|
|
|
|
|
|
MMG$GL_RESERVED_SVAPTE
|
MMG$GQ_WINDOW_PTE_PFN
|
64-bit pointer to PFN field of first reserved PTE.
|
|
|
|
|
|
MMG$GL_RESERVED_SVAPTE2
|
MMG$GQ_WINDOW2_PTE_PFN
|
64-bit pointer to PFN field of second reserved PTE.
|
|
|
|
|
|
MMG$GL_SHARED_L2PT_PFN
|
None
|
This cell was deleted since it is possible to have more than one shared
L2PT. That is system space may span over multiple L2PTs.
|
|
|
|
|
|
MMG$GL_SPT_L2PTE_BIAS
|
None
|
This cell was deleted since it is possible to have more than one shared
L2PT. That is system space may span over multiple L2PTs.
|
|
|
|
|
|
MMG$GL_VA_TO_PX_VPN
|
None
|
This data cell has been completely obviated by the removal of the
process page tables from the balance slot.
|
|
|
|
|
|
MMG$GL_ZERO_SVA
|
MMG$GQ_WINDOW_VA
|
Increased in length to quadword.
|
|
|
|
|
|
MMG$GL_ZERO_SVAPTE_PFN
|
MMG$GQ_WINDOW_PTE_PFN
|
64-bit pointer to PFN field of reserved PTE.
|
|
|
|
|
|
MMG$GQ_PT_VA
|
MMG$GQ_PT_BASE
|
MMG$GQ_PT_VA was renamed to ensure that any code that had assumed a
fixed location of page table space as a function of page size would be
revisited. The location of page table space is now variable to meet the
individual bootstrap needs of supporting Version 7.0, as well as being
a function of the page size.
|
|
|
|
|
|
MPW$GW_HILIM
|
MPW$GL_HILIM
|
Increased in length to a longword.
|
|
|
|
|
|
MPW$GW_LOLIM
|
MPW$GL_LOLIM
|
Increased in length to a longword.
|
|
|
|
|
|
PFN$GB_LENGTH
|
None
|
|
|
|
|
|
|
PFN$PL_DATABASE
|
PFN$PQ_DATABASE
|
The PFN database was moved to S2 space, which is only addressable with
64-bit pointers.
|
|
|
|
|
|
PHV$GL_REFCBAS
|
PHV$GL_REFCBAS_LW
|
The process header reference count vector has been promoted from an
array of words to an array of longwords.
|
|
|
|
|
|
SGN$GL_PHDAPCNT
|
None
|
This cell was deleted as a result of moving the process page tables out
of the balance slot.
|
|
|
|
|
|
SGN$GL_PHDP1WPAG
|
None
|
This cell was deleted as a result of moving the process page tables out
of the balance slot.
|
|
|
|
|
|
SGN$GL_PHDRESPAG
|
None
|
This cell was deleted as a result of moving the process page tables out
of the balance slot.
|
|
|
|
|
|
SGN$GL_PTPAGCNT
|
None
|
This cell was deleted as a result of moving the process page tables out
of the balance slot.
|
|
|
|
|
|
SWP$GL_L1PT_SVAPTE
|
None
|
L1 page table now mapped virtually in page table space.
|
|
|
|
|
|
SWP$GL_L1PT_VA
|
None
|
L1 page table now mapped virtually in page table space.
|
|
|
|
|
|
SWP$GW_BAKPTE
|
None
|
This cell was deleted as a result of moving the process page tables out
of the balance slot.
|
