HP OpenVMS Systems Documentation
HP OpenVMS MACRO Compiler
Porting and User's Guide
Begin
Index
Contents (summary)
Preface
Preface
Part 1
Concepts and Methodology
Chapter 1
Preparing to Port Macro-32 Code
Chapter 2
How the MACRO Compiler Functions on Different Platforms
Chapter 3
Recommended and Required Source Changes
Chapter 4
Improving the Performance of Ported Code
Chapter 5
MACRO Support for 64-Bit Addressing
Part 2
Reference
Appendix A
MACRO Compiler Qualifiers
Appendix B
Specialized Directives
Appendix C
MACRO Compiler Built-Ins
Appendix D
Macros for Porting from VAX to Alpha or I64
Appendix E
Macros for 64-Bit Addressing
Index
Examples
Tables
Contents
Preface
Preface
Preface
Part 1
Part 1
Concepts and Methodology
Chapter 1
1
Preparing to Port Macro-32 Code
1.1
Features of the MACRO Compiler
1.2
Differences Between the Compiler and the Assembler
1.2.1
Moving Code
1.2.2
Replicating Code
1.2.3
Removing Code
1.2.4
Interleaving Instructions
1.2.5
Reserved Operand Faults
1.3
Step-by-Step Porting Process for OpenVMS VAX to OpenVMS Alpha or OpenVMS I64
1.4
Step-by-Step Porting Process for OpenVMS Alpha to OpenVMS I64
1.5
Identifying Nonportable VAX MACRO Coding Practices
1.6
Establishing Useful Coding Conventions
1.7
Maintaining Common Sources
1.7.1
Including Compiler Directive Definitions
1.7.2
Removing VAX Dependencies
1.7.3
Conditionalizing Architecture-Specific Code
Chapter 2
2
How the MACRO Compiler Functions on Different Platforms
2.1
Using Alpha and Itanium Registers
2.2
Itanium Architecture, Calling Standard, and Register Mapping
2.3
Routine Calls and Declarations
2.3.1
Linkage Section (OpenVMS Alpha only)
2.3.2
Prologue and Epilogue Code
2.3.3
When to Declare Entry Points
2.3.4
Directives for Designating Routine Entry Points
2.3.5
Code Generation for Routine Calls
2.4
Declaring CALL Entry Points
2.4.1
Homed Argument Lists
2.4.2
Saving Modified Registers
2.4.3
Modifying the Argument Pointer
2.4.4
Establishing Dynamic Condition Handlers in Called Routines
2.5
Declaring JSB Routine Entry Points
2.5.1
Differences Between .JSB_ENTRY and .JSB32_ENTRY
2.5.2
Two General Cases for Using .JSB32_ENTRY
2.5.3
PUSHR and POPR Instructions Within JSB Routines
2.5.4
Establishing Dynamic Condition Handlers in JSB Routines
2.6
Declaring a Routine's Register Use
2.6.1
Input Argument for Entry Point Register Declaration
2.6.2
Output Argument for Entry Point Register Declaration
2.6.3
Scratch Argument for Entry Point Register Declaration
2.6.4
Preserve Argument for Entry Point Register Declaration
2.6.5
Help for Specifying Register Sets
2.7
Branching Between Local Routines
2.8
Declaring Exception Entry Points (OpenVMS Alpha only)
2.9
Using Packed Decimal Instructions
2.9.1
Differences Between the OpenVMS VAX and OpenVMS Alpha/I64 Implementations
2.10
Using Floating-Point Instructions
2.10.1
Differences Between the OpenVMS VAX and OpenVMS Alpha/I64 Implementations
2.10.2
Impact on Routines in Other Languages
2.11
Preserving VAX Atomicity and Granularity
2.11.1
Preserving Atomicity
2.11.2
Preserving Granularity
2.11.3
Precedence of Atomicity Over Granularity
2.11.4
When Atomicity Cannot Be Guaranteed
2.11.5
Alignment Considerations for Atomicity
2.11.6
Interlocked Instructions and Atomicity
2.12
Compiling and Linking
2.12.1
Line Numbering in Listing File
2.13
Debugging
2.13.1
Code Relocation
2.13.2
Symbolic Variables for Routine Arguments
2.13.3
Locating Arguments Without $ARG
n
Symbols
2.13.3.1
Additional Arguments That Are Easy to Locate
2.13.3.2
Additional Arguments That Are Not Easy to Locate
2.13.4
Using VAX and Alpha Register Names on OpenVMS I64
2.13.5
Debugging Code with Packed Decimal Data
2.13.6
Debugging Code with Floating-Point Data
Chapter 3
3
Recommended and Required Source Changes
3.1
Stack Usage
3.1.1
References to the Procedure Stack Frame
3.1.2
References Outside the Current Stack Frame
3.1.3
Nonaligned Stack References
3.1.4
Building Data Structures on the Stack
3.1.5
Quadword Moves Into the VAX SP and PC
3.2
Instruction Stream
3.2.1
Data Embedded in the Instruction Stream
3.2.2
Run-Time Code Generation
3.2.3
Dependencies on Instruction Size
3.2.4
Incomplete Instructions
3.2.5
Untranslatable VAX Instructions
3.2.6
References to Internal Processor Registers
3.2.7
Use of Z and N Condition Codes with the BICPSW Instruction
3.2.8
Interlocked Memory Instructions
3.2.9
Use of the MOVPSL Instruction
3.2.10
Instructions Implemented By Macros
3.3
Flow Control Mechanisms
3.3.1
Communication by Condition Codes
3.3.2
Branches from JSB Routines into CALL Routines
3.3.3
Pushing a Return Address onto the Stack
3.3.4
Removing the Return Address from the Stack
3.3.5
Modifying the Return Address
3.3.6
Coroutine Calls
3.3.7
Using REI to Change Modes
3.3.8
Loop Nesting Limit
3.4
Dynamic Image Relocation
3.5
Overwriting Static Data
3.6
Static Initialization Using External Symbols
3.7
Transfer Vectors
3.8
Arithmetic Exceptions
3.9
Page Size
3.10
Locking Pages into a Working Set
3.11
Synchronization
Previous
Next
Contents
Index