Table 3-3 Removed System Data Cells
| Removed Cell |
Replacement |
Comments |
| CTL$AL_STACK |
CTL$AQ_STACK |
Arrays are now quadwords. |
| |
|
|
| CTL$AL_STACKLIM |
CTL$AQ_STACKLIM |
Arrays are now quadwords. |
| |
|
|
| EXE$GL_GPT |
MMG$GQ_FREE_GPT |
As of Version 7.0, free GPTEs are managed in the same manner as free
system PTEs. Note that 64-bit virtual addresses are required to access
GPTEs. |
| |
|
|
| LDR$GL_FREE_PT |
LDR$GQ_FREE_S0S1_PT |
Contains the address of the start of the free S0/S1 PTE list. The format
of the free PTEs has changed for Version 7.0. |
| |
|
|
| MMG$GL_FRESVA |
MMG$GQ_NEXT_FREE_S0S1_VA |
|
| |
|
|
| MMG$GL_GPTBASE |
MMG$GQ_GPT_BASE |
As of Version 7.0, free GPTEs are managed in the same manner as free
system PTEs. Note that 64-bit virtual addresses are required to access
GPTEs. |
| |
|
|
| MMG$GL_MAXGPTE |
MMG$GQ_MAX_GPTE |
As of Version 7.0, free GPTEs are managed in the same manner as free
system PTEs. Note that 64-bit virtual addresses are required to access
GPTEs. |
| |
|
|
| MMG$GL_P0_PTLEN |
None |
Obviated by the removal of the process page tables from the balance
slot. |
| |
|
|
| MMG$GL_PX_VPN_LENGTH |
None |
This data cell is obviated by the removal of the process page tables
from the balance slot. |
| |
|
|
| MMG$GL_RESERVED_SVA |
MMG$GQ_WINDOW_VA |
Increased in length to quadword. |
| |
|
|
| MMG$GL_RESERVED_SVA2 |
MMG$GQ_WINDOW2_VA |
Increased in length to quadword. |
| |
|
|
| MMG$GL_RESERVED_SVAPTE |
MMG$GQ_WINDOW_PTE_PFN |
64-bit pointer to PFN field of first reserved PTE. |
| |
|
|
| MMG$GL_RESERVED_SVAPTE2 |
MMG$GQ_WINDOW2_PTE_PFN |
64-bit pointer to PFN field of second reserved PTE. |
| |
|
|
| MMG$GL_SHARED_L2PT_PFN |
None |
This cell was deleted since it is possible to have more than one shared
L2PT. That is system space may span over multiple L2PTs. |
| |
|
|
| MMG$GL_SPT_L2PTE_BIAS |
None |
This cell was deleted since it is possible to have more than one shared
L2PT. That is system space may span over multiple L2PTs. |
| |
|
|
| MMG$GL_VA_TO_PX_VPN |
None |
This data cell has been completely obviated by the removal of the process
page tables from the balance slot. |
| |
|
|
| MMG$GL_ZERO_SVA |
MMG$GQ_WINDOW_VA |
Increased in length to quadword. |
| |
|
|
| MMG$GL_ZERO_SVAPTE_PFN |
MMG$GQ_WINDOW_PTE_PFN |
64-bit pointer to PFN field of reserved PTE. |
| |
|
|
| MMG$GQ_PT_VA |
MMG$GQ_PT_BASE |
MMG$GQ_PT_VA was renamed to ensure that any code that had assumed a
fixed location of page table space as a function of page size would be
revisited. The location of page table space is now variable to meet the
individual bootstrap needs of supporting Version 7.0, as well as being
a function of the page size. |
| |
|
|
| MPW$GW_HILIM |
MPW$GL_HILIM |
Increased in length to a longword. |
| |
|
|
| MPW$GW_LOLIM |
MPW$GL_LOLIM |
Increased in length to a longword. |
| |
|
|
| PFN$GB_LENGTH |
None |
|
| |
|
|
| PFN$PL_DATABASE |
PFN$PQ_DATABASE |
The PFN database was moved to S2 space, which is only addressable with
64-bit pointers. |
| |
|
|
| PHV$GL_REFCBAS |
PHV$GL_REFCBAS_LW |
The process header reference count vector has been promoted from an
array of words to an array of longwords. |
| |
|
|
| SGN$GL_PHDAPCNT |
None |
This cell was deleted as a result of moving the process page tables
out of the balance slot. |
| |
|
|
| SGN$GL_PHDP1WPAG |
None |
This cell was deleted as a result of moving the process page tables
out of the balance slot. |
| |
|
|
| SGN$GL_PHDRESPAG |
None |
This cell was deleted as a result of moving the process page tables
out of the balance slot. |
| |
|
|
| SGN$GL_PTPAGCNT |
None |
This cell was deleted as a result of moving the process page tables
out of the balance slot. |
| |
|
|
| SWP$GL_L1PT_SVAPTE |
None |
L1 page table now mapped virtually in page table space. |
| |
|
|
| SWP$GL_L1PT_VA |
None |
L1 page table now mapped virtually in page table space. |
| |
|
|
| SWP$GW_BAKPTE |
None |
This cell was deleted as a result of moving the process page tables
out of the balance slot. |
