Jane C. Blake,
Managing Editor

The NVAX microprocessor is a high-performance, single-chip implementation of the VAX architecture. It is today's fastest VAX microprocessor and the CPU at the heart of the mid-range, low-end, and workstation systems described in this issue of the Digital Technical Journal.

The NVAX chip is not only fast, with cycle times as low as 11 ns, but also holds a unique position in the Digital family of microprocessors: NVAX is both an upgrade path for existing VAX systems and a migration path to Alpha AXP systems. In their paper on the NVAX and NVAX+ chips, Mike Uhler, Debra Bernstein, Larry Biro, John Brown, John Edmondson, Jeff Pickholtz, and Rebecca Stamm present an overview of the complex microprocessor designs and relate how RISC techniques are used in this CISC machine to achieve dramatic increases in performance over previous implementations.

Increases in performance are also attributable to the CMOS-4 0.75- micrometer process technology in which the NVAX is implemented. In their paper about the verification of the physical design, Dale Donchin, Tim Fischer, Frank Fox, Victor Peng, Ron Preston, and Bill Wheeler describe the methods and the CAD tools created to manage the complexity of a chip with 1.3 million transistors.

The rigorous use of the CAD tools and thorough simulation-based testing resulted in highly functional first-pass chips. In his paper about the logical verification, Walker Anderson discusses the successful strategies used to ensure no "show stopper" bugs existed in the design. Highlighting major strategies, he reviews the behavioral models and pseudorandom exercisers at the core of the verification effort.

Each system design team chose a different approach to take advantage of NVAX performance and to meet system-specific requirements. In a paper on the new mid-range VAX 6000 multiprocessing system, Larry Chisvin, Gregg Bouchard, and Tom Wenners explain the module design decisions that supported the goals of 6000-series compatibility and time to market. Of particular interest are the schedule and performance benefits derived from developing a routing and control interface chip.

The engineers for new low-end deskside systems also chose to develop custom chips-a memory controller chip, memory module, and an I/O controller. Jon Crowell, Kwong Chui, Tom Kopec, Sam Nadkarni, and Dean Sovie discuss the chip functions that were key to exceeding the performance goal of three times that of the previous VAX 4000.

For the low-end VAX 4000 Model 100 system and the MicroVAX 3100 desktop servers, designers saved significant time by "borrowing" existing components from proven systems. Jon Crowell and Dave Maruska relate decisions that allowed them to double performance and complete the work within the extraordinarily short time of nine months.

The newest VAXstation workstation, based on NVAX, is the Model 90. Mike Callander, Lauren Carlson, Andy Ladd, and Mitch Norcross present their design methodology. Most significant for development was the decision to implement new logic in programmable technology, which allowed bug fixes in minutes rather than weeks.

Not about system design but rather error handling in 6000 systems, Brian Porter's paper describes an approach that reduces the amount of unique coding traditionally required for error handling. He details the development of sophisticated error handling routines that accommodate the complexity of the symmetric multiprocessing VAX 6000 models.

The editors thank Mike Uhler of the Semiconductor Engineering Group, who ensured that the standards of excellence applied to NVAX development were applied to the development of this issue. Also, this issue is notable editorially because it is the first in which papers have been formally refereed. I thank Gene Hoffnagle, editor of the IBM Systems Journal, for encouraging the use of the referee process in any journal worthy of the name. DTJ issues will continue to be refereed so that we may offer engineering and academic readers informative and relevant technical discussions.