Managers,
I have an AlphaStation 255 running DU4.0D with 256M of Dataram memory in
Bank0. One or more of the boards seems to be bad. My question is:
which one?
I checked the archives and found the firmware memory test post, but it
didn't help. The command memory, in particular, fails saying that echo
and memtest aren't found. I upgraded the firmware, but this didn't help.
I've also moved the memory from another 255 which is identical aside
from running an earlier version of the OS. The problem follows the
memory, and unfortunatlely I don't have another set of boards to swap one
at a time to trace the problem.
I called Digital and they were able to run a script (which they weren't
willing to part with--of course I asked :>) which gave me the jumper
location. I replaced the board, and all was apparently well for a
while. It now seems that things are better, but not fixed, as if two
boards were bad and the worst has been replaced. These errors do cause
panics, so it's important that I get this fixed, and soon. Naturally
these crashes come during the big memory intensive jobs that you least
want to crash.
The output of dia -o full is below for two of these events. The last is
the most recent. I'm sure the answer is there, and while I can make a
guess, I need a definitive answer, and better yet, directions on how to
derive it myself. I want to shuffle the boards once I know which is bad
and verify that the error moves with a single board.
I'd also like to find in-depth information on Alpha hardware, whether in
digital or paper form. I searched Digital's web site and found a lot of
promotional materials, but nothing on the "nuts and bolts" level.
Recommendations welcome. :)
Many thanks in advance, and I will post a summary.
Rob McCauley, the .sig-less
dia -o full (version 2.6) output follows:
******************************** ENTRY 1 ********************************
Logging OS 2. Digital UNIX
System Architecture 2. Alpha
Event sequence number 24.
Timestamp of occurrence 18-MAR-1998 15:33:36
Host name reynolds
System type register x0000000D AlphaStation 400 or 2xx
Number of CPUs (mpnum) x00000001
CPU logging event (mperr) x00000000
Event validity 1. O/S claims event is valid
Event severity 1. Severe Priority
Entry type 100. CPU Machine Check Errors
CPU Minor class 1. Machine check (670 entry)
Byte Count x02E8
Processor Specific Offset x00000110
System Specific Offset x000001A0
PAL Error Type Code x00000092 D-Cache Parity Error
PAL Frame Revision x00000001
- ALPHA CHIP REGISTERS -
PALTEMP1 x000000014E798E00
PALTEMP2 x001386F800000004
PALTEMP3 x0000000000000003
PALTEMP4 x000000014E798E00
PALTEMP5 x0000000149A0E010
PALTEMP6 xFFFFFC0000453108
PALTEMP7 x0000000000004200
PALTEMP8 x0000000000000400
PALTEMP9 x0000000000000000
PALTEMP10 xFFFFFC000042E040
PALTEMP11 x0000000000000000
PALTEMP12 xFFFFFC000042E410
PALTEMP13 xFFFFFC000042E440
PALTEMP14 xFFFFFC000042E4A0
PALTEMP15 xFFFFFC000042E1E0
PALTEMP16 xFFFFFC000042DDC0
PALTEMP17 x000000014DBAA8F8
PALTEMP18 x000000011FFFF760
PALTEMP19 xFFFFFFFF90383A38
PALTEMP20 xFFFFFC00005A1CB0
PALTEMP21 xFFFFFC00005A2D48
PALTEMP22 x00505070727A7A7A
PALTEMP23 xFFFFFC00001F2100
PALTEMP24 x0000000000000000
PALTEMP25 x0000000000010000
PALTEMP26 x000000000000E16F
PALTEMP27 x0000000000000000
PALTEMP28 x0000000000230000
PALTEMP29 xFFFFFFFC00000000
PALTEMP30 xFFFFFC00001F2114
PALTEMP31 x000000000A557A38
Exception Address Reg x0000000120004D02
Exception Address Reg Provides Information
About The Most Recent Exception.
Address Points to Native-Mode Instruction
If Machine Check or Math Trap Exception,
PC in Exception Address is Correct.
Last Exception Addr PC: x0000000048001340
Exception Summary Reg x0000000000000000
Exception Mask Reg x0000000000000000
Icache Ctrl & Status Reg x001386F800000004
Performance Counters Disabled
Empty Wrt Buffer Before Issuing Next Inst
Branch Prediction Selection: Not Taken
JSR Stack is Disabled
Instructions Can Only Single Issue
If Not in PALmode, Executing Reserved Inst
Opcode Will Result in OPCDEC Exception.
Super Page Istream Memory Mapping Disabled
Float Point Inst Will Cause FEN Exception
Icache Addr Space Numb: x0000000000000000
PALcode Base Address Reg x0000000000014000
PALcode Base Address: x0000000000000005
Hardware Int Enable Reg x00000000000014F0
CRD Error Interrupts Enabled
CPU Hrdw Interrupts Enabled Irq_h Pins 0,2
CPU Hrdw Interrupts Enbld Irq_h Pins 3,4,5
Performance Cntr 0 & 1 Interrupts Disabled
Serial Line Interrupts Disabled
NO AST Interrupts Enabled In Any Mode
Hardware Int Request Reg x0000000000000000
NO Hrdw Int Req With Companion Enable Set
NO Softw Int Req With Companion Enable Set
NO AST Int Req With Companion Enable Set
Memory Management CSR x00000000000046E0
MMCSR Valid Only on Mem Mgt Err, DTB Miss,
D-Stream Fault, Dcache Parity Error.
Last Faulting Instruction RA Field: R14
Last Faulting Instruction Opcode Follows:
x23 - LDT Load T_floating
(Data) Cache Status Reg x0000000000000003
This is EV45 Cache Status Register(C_STAT)
EV45 Chip is Production Version of 21064A
Last Load or Store Missed Dcache
Cache Address Reg x00000007FFFFFFFF
Abox Control Reg x000000000000942E
Machine Checks Enabled for Uncorr Errors
CRD Interrupts Enabled
Single Entry Icache Stream Buffer Enabled
Enable Super Page Dstream Virtual Addr Map
VA<33:13> to PA<33:13>, if VA<42:41>=2.
Lock Operation Conforms to Alpha Architect
Dcache Enabled
16K Byte Dcache Selected
Double Invalidate: Both EV45 Dcache Blocks
Addressed By iAdr_h<12:5> Invalidated.
Bus Interface Status Reg x0000000000003440
PARITY ERROR In QW3 of Primary Cache Fill
Block Hexaword During a Dcache Fill.
Bus Interface Address Reg x0000000008C4E8E0
Address Only Valid if Bus Interface Status
Register Error Bit 0,1,2, or 3 is Set.
BIU Addr adr_h<33:5>: x0000000000462747
Bus Interface Control Reg x0000000810002225
External Cache (Bcache) Enabled
PARITY MODE: External Cache Parity Enabled
Cache Rams are Output Enable Controlled
Ext Cache Rd Access Time: 3 CPU Cycles
Ext Cache Wrt Cycle Time: 3 CPU Cycles
Size of External Cache: 256 Kbyte
Ext Cache For Phys Addr Quad 3 Disabled
Ext Cache Rd Time Controlling Bcache Reads
Ext Cache Wrt En Ctrl: x0000000000000001
Fill Syndrome Reg x0000000000000001
IF ECC MODE (Bus Intf Ctl Reg Bit 1 Set),
Low LW of Quadword Check Bit 00 Err.
IF PARITY MODE(Bus Intf Ctl Reg Bit 1 Clr)
Low LW of Quadword Corrupted.
No Error in Upper Long Word of Quad Word
Fill Address Reg x0000000008C4E8E0
Addr Only Valid if Bus Interface Stat Reg
ECC(Bit 8) or PARITY(Bit 10) Error Set.
Cache Blk Phy Adr<33:5> x0000000000462747
Virtual Address Reg x0000000000006170
Dstream FLT/DTB Miss VA x0000000000006170
Bcache Tag Reg x000000000040EF12
Last Bcache Access Resulted in a Miss
Parity Bit for Bcache Tag Status Bits Set
Bcache Tag Dirty Bit Clear
Bcache Tag Shared Bit Clear
Bcache Tag Valid Bit Set
Bcache Tag Addrress Parity Bit Asserted
Tag Being Probed: x0000000000000778
coma_gcr x000000007FB200B4
DMA Priority
128 bit wide MEM
Bcache enabled
Bcache long writes
coma_edsr x000000007FB22000
coma_ter x000000006FB13FF0
sysTag<21:17> = x0000000000001FF8
coma_elar x000000006FB10000
sysBus<20:5> at time of e x0000000000000000
coma_ehar x000000006FB109B0
sysBus<33:21> at time of x00000000000009B0
coma_ldlr x000000006FB13485
sysBus<20:5> last locked x0000000000003485
coma_ldhr x000000006FB10055
sysBus<31:21> last locked x0000000000000055
coma_base0 x000000006FB10000
Reg Base Adr <33:23> = x0000000000000000
coma_base1 x000000006FB10000
Reg Base Adr <33:23> = x0000000000000000
coma_base2 x0000000047FF0000
Reg Base Adr <33:23> = x0000000000000000
coma_cnfg0 x0000000047FF0005
Bank Valid
Bank Size = 256 MB
Column Adr Selection x0000000000000000
coma_cnfg1 x0000000047FF0000
Bank Size = 1024 MB
Column Adr Selection x0000000000000000
coma_cnfg2 x0000000047FF0000
Bank Size = 1024 MB
Column Adr Selection x0000000000000000
epic_dcsr xFFFFFFFF800E001D
Translation buffer enabled
Prefetch enabled
Disable correctable error
Pass 2 Chip
Partial Bypass
PCI Cycle Type = IO Write
epic_pear x0000000000805560
PCI error address x0000000000805560
epic_sear x0000000003FD6560
DMA Address = x00000000003FD656
epic_tbr1 x00000000005D6000
Translation Base Adr = x0000000000002EB0
epic_tbr2 x0000000000000000
Translation Base Adr = x0000000000000000
epic_pbr1 x00000000008C0000
Scatter/Gather Enabled
Window Enabled
PCI Base Adr x0000000000000008
epic_pbr2 x0000000040080000
Scatter/Gather Disabled
Window Enabled
PCI Base Adr x0000000000000400
epic_pmr1 x0000000000700000
PCI Mask x0000000000000007
epic_pmr2 x000000003FF00000
PCI Mask x00000000000003FF
epic_harx1 xFFFFFFFF80000000
PCI_ad - memory space = x0000000000000010
epic_harx2 x0000000000000000
PCI_ad - memory space = x0000000000000000
epic_pmlt x00000000000000FF
Master Latency Timer = 255.
epic_tag0 x0000000000807000
Entry Valid
pci_page x0000000000000101
epic_tag1 x0000000000805000
Entry Valid
pci_page x0000000000000100
epic_tag2 x0000000000806000
pci_page x0000000000000101
epic_tag3 x0000000000804000
pci_page x0000000000000100
epic_tag4 x0000000000812000
pci_page x0000000000000103
epic_tag5 x0000000000814000
pci_page x0000000000000102
epic_tag6 x0000000000803000
Entry Valid
pci_page x0000000000000101
epic_tag7 x0000000000801000
Entry Valid
pci_page x0000000000000100
epic_data0 x00000000000005C2
cpu_page x0000000000000170
epic_data1 x00000000000005C0
cpu_page x0000000000000170
epic_data2 x00000000000005C2
cpu_page x0000000000000170
epic_data3 x00000000000005C0
cpu_page x0000000000000170
epic_data4 x000000000000EB3C
cpu_page x0000000000003ACF
epic_data5 x000000000000C53A
cpu_page x000000000000314E
epic_data6 x00000000000005BE
cpu_page x000000000000016F
epic_data7 x00000000000005BC
cpu_page x000000000000016F
******************************** ENTRY 31 ********************************
Logging OS 2. Digital UNIX
System Architecture 2. Alpha
Event sequence number 11.
Timestamp of occurrence 23-MAR-1998 13:18:36
Host name reynolds
System type register x0000000D AlphaStation 400 or 2xx
Number of CPUs (mpnum) x00000001
CPU logging event (mperr) x00000000
Event validity 1. O/S claims event is valid
Event severity 1. Severe Priority
Entry type 100. CPU Machine Check Errors
CPU Minor class 1. Machine check (670 entry)
Byte Count x02E8
Processor Specific Offset x00000110
System Specific Offset x000001A0
PAL Error Type Code x00000092 D-Cache Parity Error
PAL Frame Revision x00000001
- ALPHA CHIP REGISTERS -
PALTEMP1 x000000014A0528F0
PALTEMP2 x001586F800000004
PALTEMP3 x000000014A055F30
PALTEMP4 x00000000000FA895
PALTEMP5 x000000014A056110
PALTEMP6 x0000000000000000
PALTEMP7 x0000000000004200
PALTEMP8 x0000000000000400
PALTEMP9 x0000000000000000
PALTEMP10 xFFFFFC000042E040
PALTEMP11 x0000000000000000
PALTEMP12 xFFFFFC000042E410
PALTEMP13 xFFFFFC000042E440
PALTEMP14 xFFFFFC000042E4A0
PALTEMP15 xFFFFFC000042E1E0
PALTEMP16 xFFFFFC000042DDC0
PALTEMP17 x0000000000000000
PALTEMP18 x000000011FFFF7B0
PALTEMP19 xFFFFFFFF90393A38
PALTEMP20 xFFFFFC00005A1CB0
PALTEMP21 xFFFFFC00005A2D48
PALTEMP22 x00505070727A7A7A
PALTEMP23 xFFFFFC00001F2100
PALTEMP24 x0000000000000000
PALTEMP25 x0000000000010000
PALTEMP26 x000000000000C3DD
PALTEMP27 x0000000000000000
PALTEMP28 x000000000820E000
PALTEMP29 xFFFFFFFC00000000
PALTEMP30 xFFFFFC00001F2114
PALTEMP31 x0000000003D41A38
Exception Address Reg x0000000120012492
Exception Address Reg Provides Information
About The Most Recent Exception.
Address Points to Native-Mode Instruction
If Machine Check or Math Trap Exception,
PC in Exception Address is Correct.
Last Exception Addr PC: x0000000048004924
Exception Summary Reg x0000000000000000
Exception Mask Reg x0000000000000000
Icache Ctrl & Status Reg x001586F800000004
Performance Counters Disabled
Empty Wrt Buffer Before Issuing Next Inst
Branch Prediction Selection: Not Taken
JSR Stack is Disabled
Instructions Can Only Single Issue
If Not in PALmode, Executing Reserved Inst
Opcode Will Result in OPCDEC Exception.
Super Page Istream Memory Mapping Disabled
Float Point Inst Will Cause FEN Exception
Icache Addr Space Numb: x0000000000000000
PALcode Base Address Reg x0000000000014000
PALcode Base Address: x0000000000000005
Hardware Int Enable Reg x00000000000014F0
CRD Error Interrupts Enabled
CPU Hrdw Interrupts Enabled Irq_h Pins 0,2
CPU Hrdw Interrupts Enbld Irq_h Pins 3,4,5
Performance Cntr 0 & 1 Interrupts Disabled
Serial Line Interrupts Disabled
NO AST Interrupts Enabled In Any Mode
Hardware Int Request Reg x0000000000000000
NO Hrdw Int Req With Companion Enable Set
NO Softw Int Req With Companion Enable Set
NO AST Int Req With Companion Enable Set
Memory Management CSR x0000000000004720
MMCSR Valid Only on Mem Mgt Err, DTB Miss,
D-Stream Fault, Dcache Parity Error.
Last Faulting Instruction RA Field: R18
Last Faulting Instruction Opcode Follows:
x23 - LDT Load T_floating
(Data) Cache Status Reg x0000000000000003
This is EV45 Cache Status Register(C_STAT)
EV45 Chip is Production Version of 21064A
Last Load or Store Missed Dcache
Cache Address Reg x00000007FFFFFFFF
Abox Control Reg x000000000000942E
Machine Checks Enabled for Uncorr Errors
CRD Interrupts Enabled
Single Entry Icache Stream Buffer Enabled
Enable Super Page Dstream Virtual Addr Map
VA<33:13> to PA<33:13>, if VA<42:41>=2.
Lock Operation Conforms to Alpha Architect
Dcache Enabled
16K Byte Dcache Selected
Double Invalidate: Both EV45 Dcache Blocks
Addressed By iAdr_h<12:5> Invalidated.
Bus Interface Status Reg x0000000000003440
PARITY ERROR In QW3 of Primary Cache Fill
Block Hexaword During a Dcache Fill.
Bus Interface Address Reg x0000000008C4E8F0
Address Only Valid if Bus Interface Status
Register Error Bit 0,1,2, or 3 is Set.
BIU Addr adr_h <4:2>: x4
BIU Addr adr_h<33:5>: x0000000000462747
Bus Interface Control Reg x0000000810002225
External Cache (Bcache) Enabled
PARITY MODE: External Cache Parity Enabled
Cache Rams are Output Enable Controlled
Ext Cache Rd Access Time: 3 CPU Cycles
Ext Cache Wrt Cycle Time: 3 CPU Cycles
Size of External Cache: 256 Kbyte
Ext Cache For Phys Addr Quad 3 Disabled
Ext Cache Rd Time Controlling Bcache Reads
Ext Cache Wrt En Ctrl: x0000000000000001
Fill Syndrome Reg x0000000000000001
IF ECC MODE (Bus Intf Ctl Reg Bit 1 Set),
Low LW of Quadword Check Bit 00 Err.
IF PARITY MODE(Bus Intf Ctl Reg Bit 1 Clr)
Low LW of Quadword Corrupted.
No Error in Upper Long Word of Quad Word
Fill Address Reg x0000000008C4E8F0
Addr Only Valid if Bus Interface Stat Reg
ECC(Bit 8) or PARITY(Bit 10) Error Set.
IF Bus Interface Stat Reg FILL_IRD Bit 11
is Clear, Cache Blk Phy Adr<4:2> is: x4
Cache Blk Phy Adr<33:5> x0000000000462747
Virtual Address Reg x0000000000006170
Dstream FLT/DTB Miss VA x0000000000006170
Bcache Tag Reg x000000000000D412
Last Bcache Access Resulted in a Miss
Parity Bit for Bcache Tag Status Bits Set
Bcache Tag Dirty Bit Clear
Bcache Tag Shared Bit Clear
Bcache Tag Valid Bit Set
Bcache Tag Addrress Parity Bit Clear
Tag Being Probed: x00000000000006A0
coma_gcr x000000007FB200B4
DMA Priority
128 bit wide MEM
Bcache enabled
Bcache long writes
coma_edsr x000000007FB22000
coma_ter x000000006FB13FF0
sysTag<21:17> = x0000000000001FF8
coma_elar x000000006FB10000
sysBus<20:5> at time of e x0000000000000000
coma_ehar x000000006FB109B0
sysBus<33:21> at time of x00000000000009B0
coma_ldlr x000000006FB1F937
sysBus<20:5> last locked x000000000000F937
coma_ldhr x000000006FB10000
sysBus<31:21> last locked x0000000000000000
coma_base0 x000000006FB10000
Reg Base Adr <33:23> = x0000000000000000
coma_base1 x000000006FB10000
Reg Base Adr <33:23> = x0000000000000000
coma_base2 x0000000047FF0000
Reg Base Adr <33:23> = x0000000000000000
coma_cnfg0 x0000000047FF0005
Bank Valid
Bank Size = 256 MB
Column Adr Selection x0000000000000000
coma_cnfg1 x0000000047FF0000
Bank Size = 1024 MB
Column Adr Selection x0000000000000000
coma_cnfg2 x0000000047FF0000
Bank Size = 1024 MB
Column Adr Selection x0000000000000000
epic_dcsr xFFFFFFFF800E001D
Translation buffer enabled
Prefetch enabled
Disable correctable error
Pass 2 Chip
Partial Bypass
PCI Cycle Type = IO Write
epic_pear x0000000000805620
PCI error address x0000000000805620
epic_sear x0000000003FD6540
DMA Address = x00000000003FD654
epic_tbr1 x00000000005D6000
Translation Base Adr = x0000000000002EB0
epic_tbr2 x0000000000000000
Translation Base Adr = x0000000000000000
epic_pbr1 x00000000008C0000
Scatter/Gather Enabled
Window Enabled
PCI Base Adr x0000000000000008
epic_pbr2 x0000000040080000
Scatter/Gather Disabled
Window Enabled
PCI Base Adr x0000000000000400
epic_pmr1 x0000000000700000
PCI Mask x0000000000000007
epic_pmr2 x000000003FF00000
PCI Mask x00000000000003FF
epic_harx1 xFFFFFFFF80000000
PCI_ad - memory space = x0000000000000010
epic_harx2 x0000000000000000
PCI_ad - memory space = x0000000000000000
epic_pmlt x00000000000000FF
Master Latency Timer = 255.
epic_tag0 x0000000000806000
pci_page x0000000000000101
epic_tag1 x0000000000804000
pci_page x0000000000000100
epic_tag2 x0000000000803000
Entry Valid
pci_page x0000000000000101
epic_tag3 x0000000000801000
Entry Valid
pci_page x0000000000000100
epic_tag4 x0000000000807000
Entry Valid
pci_page x0000000000000101
epic_tag5 x0000000000805000
Entry Valid
pci_page x0000000000000100
epic_tag6 x0000000000802000
pci_page x0000000000000101
epic_tag7 x0000000000800000
pci_page x0000000000000100
epic_data0 x00000000000005C2
cpu_page x0000000000000170
epic_data1 x00000000000005C0
cpu_page x0000000000000170
epic_data2 x00000000000005BE
cpu_page x000000000000016F
epic_data3 x00000000000005BC
cpu_page x000000000000016F
epic_data4 x00000000000005C2
cpu_page x0000000000000170
epic_data5 x00000000000005C0
cpu_page x0000000000000170
epic_data6 x00000000000005BE
cpu_page x000000000000016F
epic_data7 x00000000000005BC
cpu_page x000000000000016F
On Mon, 23 Mar 1998, Dave Sill wrote:
> EVERYONE WHO RECEIVES THIS MESSAGE HAD BETTER READ IT THOROUGHLY.
>
> Alpha-OSF-Managers Information and Rules
>
> This message is a summary of the Alpha-OSF-managers charter and rules.
> Failure to adhere to these guidelines may result in severe chastisement by
> the list maintainer and other list participants. Retain a copy of this
> statement and refer to it before submitting messages to the list or the list
> administrator.
>
> Last modified: 19980225
>
> 1. Send only Digital UNIX on Alpha systems management questions and
> summaries to alpha-osf-managers_at_ornl.gov. Include your return address
> in the body of your message so people can reply directly to you. Avoid
> MIME and HTML--many people can't read them.
>
> 2. This list is not moderated! Every message that is sent to the list will
> be passed on to every member of the list (with a few small exceptions).
>
> 3. This mailing list is managed by a utility called Majordomo. You can
> subscribe to the list by sending a message like:
>
> subscribe alpha-osf-managers
>
> to majordomo_at_ornl.gov.
>
> Likewise, if you want to remove yourself from the list, send the
> message:
>
> unsubscribe alpha-osf-managers
>
> to the same address. If that fails, examine the headers of a message
> from the list. You should see something like:
>
> From alpha-osf-managers-owner-you=your.domain_at_sws1.ctd.ornl.gov Wed Dec 31 17:02:32 1997
>
> Your subscription address is embedded in the return address after
> "alpha-osf-managers-owner-" and before "_at_sws1.ctd.ornl.gov". Just
> replace the "=" with an "_at_". Then send a message to majordomo_at_ornl.gov
> containing:
>
> unsubscribe alpha-osf-managers you_at_your.domain
>
> If you don't see anything like this, let me know and I'll see if I can
> find you on the list.
>
> For a complete list of Majordomo commands, use the command:
>
> help
>
> 4. This list is intended to be a quick-turnaround troubleshooting aid for
> those who administer and manage Alpha AXP systems runnning Digital UNIX
> (formerly OSF/1). Its primary purpose is to provide the Alpha manager
> with a quick source of information for time-critical system management
> problems.
>
> 5. This list is not available as a digest. If you don't want a bunch of
> list messages cluttering your mailbox, use procmail, deliver, or some
> other filtering mechanism to file list messages in a separate folder.
> You can also unsubscribe from the list and read it via the web
> archives.
>
> 6. Answers to questions are to be mailed back to the questioner and are
> not to be sent to the entire list. Before responding, please make sure
> the questioner hasn't already posted a summary. People often respond
> very quickly to messages posted to the list and it's not unusual for a
> summary to be posted within an hour of the original question. This is
> especially important if you only read list messages periodically.
>
> 7. The person who originally asked the question has the responsibility of
> summarizing the answers and sending the entire summary back to the
> list. Consider this the price you pay for the advice you receive. When
> a summary is sent back to the list, it should contain the word
> "SUMMARY" as the first word of the "Subject" line. The summary should
> include a brief description of the original question and a short
> synopsis of each of the unique responses. Don't just list the
> respondents or say the problem is fixed, and don't just include a copy
> of all of the responses.
>
> 8. Discussions on any topic are very strongly discouraged and will not
> normally be tolerated.
>
> 9. Unsolicited Commercial E-mail (UCE), also known as "SPAM", is, of
> course, not allowed. If you receive an inappropriate message via the
> list, feel free to complain to the originator or the originator's
> service provider. Do not post complaints to the list.
>
> 10. If it is not specifically related to Alpha AXP/Digital UNIX management,
> then it does not belong on this list. Requests for vendor
> recommendations are tolerated, provided that the hardware in question
> is something that system managers normally purchase.
>
> 11. Requests for software (free or otherwise) should be limited to software
> that is directly related to Alpha/OSF management.
>
> 12. Please...Think before you send a message! Ask yourself "is this really
> appropriate?" There are enough other newsgroups and mailing lists
> around to cover the marginal topics. Perhaps there is another forum
> that is more appropriate.
>
> 13. Alpha-OSF-Managers messages are archived and available via the World
> Wide Web (WWW):
>
> http://www.ornl.gov/cts/archives/mailing-lists/
>
> or anonymous FTP:
>
> ftp://ftp.ornl.gov/pub/archives/mailing_lists/alpha-osf-managers/
>
> European web archive is also available:
>
> http://www.rosat.mpe-garching.mpg.de/mailing-lists/Alpha-OSF-Managers/
>
> 14. Similar lists for non-Alpha/Digital UNIX platforms are:
>
> Vendor List Name How to Subscribe
> ====== ========= ================
>
> Cray unicos-l ask unicos-l-request_at_cug.org
> (CUG members only)
>
> DEC AlphaNT send "subscribe" to
> AlphaNT-request_at_listserv.mfg.mke.ab.com
>
> DEC decstation-managers send "subscribe decstation-managers"
> to majordomo_at_ornl.gov
>
> HP hpux-admin send "subscribe hpux-admin" to
> majordomo_at_cv.ruu.nl
>
> IBM AIX-L send "subscribe aix-l your name" to
> listserv_at_pucc.princeton.edu
>
> RedHat axp-list send "subscribe" to
> axp-list-request_at_redhat.com
>
> SGI info-iris ask info-iris-request_at_arl.mil
> (high volume: duplicates
> comp.sys.sgi.* newsgroups)
>
> Sun sun-managers ask sun-managers-request_at_ra.mcs.anl.gov
>
> 15. Other forums that relate to DEC Alpha systems:
>
> Newsgroups:
> comp.sys.dec includes all DEC hardware and software
> comp.unix.osf.osf1 OSF/1 on Alpha and other platforms
> comp.os.vms VMS issues for VAX and Alpha platforms
> vmsnet.alpha VMS on Alpha platforms
>
> Dave Sill
> Alpha-OSF-Managers maintainer
> Workstation Support
> Oak Ridge National Laboratory
>
Received on Tue Mar 24 1998 - 18:29:20 NZST