| Previous | Contents | Index |
Displays the multiprocessing synchronization data structures.
SHOW SPINLOCKS {[name]|/ADDRESS=expression|/INDEX=expression}
[{/BRIEF | /COUNTS | /FULL}]
[/CACHED_PCB | /DEVICE | /DYNAMIC | /MAILBOX
| /MISCELLANEOUS | /OWNED | /PCB | /PORT
| /PSHARED | /STATIC]
name
Name of the spinlock to be displayed. Device spinlock names are of the form node$lock, where node indicates the OpenVMS Cluster node name and lock indicates the device and controller identification (for example, HAETAR$DUA). If there is no OpenVMS Cluster node name, the dollar sign ($) is also skipped (for example, DUA).
/ADDRESS=expression
Displays the spinlock at the address specified in expression. You can use the /ADDRESS qualifier to display a specific device, mailbox, PCB, cached PCB, or process-shared spinlock; however, the name of the spinlock may be listed as "Unknown" in the display./BRIEF
Produces a condensed display of the spinlock information displayed by default by the SHOW SPINLOCKS command, including the following: address, spinlock name or device name, IPL or device IPL, rank, ownership depth, and CPU ID of the owner CPU. If the system under analysis was executing with full-checking multiprocessing enabled (according to the setting of the MULTIPROCESSING or SYSTEM_CHECK system parameter), then the number of waiting CPUs and interlock status are also displayed./CACHED_PCB
Displays all PCB-specific spinlocks associated with PCBs of deleted processes./COUNTS
Produces a display of Spin, Wait, and Acquire counts for each spinlock (only if full-checking multiprocessing is enabled)./DEVICE
Displays information for all device spinlocks./DYNAMIC
Displays information for all dynamic spinlocks in the system (device, port, mailbox, PCB, cached PCB, process-shared, and miscellaneous spinlocks)./FULL
Displays full descriptive and diagnostic information for each displayed spinlock./INDEX=expression
Displays the static spinlock whose index is specified in expression. You can only use the /INDEX qualifier to display a named static spinlock./MAILBOX
Displays all mailbox-specific spinlocks./MISCELLANEOUS
Display all spinlocks that are not included in existing groups such as mailbox and PCB spinlocks. Miscellaneous spinlocks include the XFC, PEDRIVER, TCP/IP, and various other spinlocks. The list of miscellaneous spinlocks varies from system to system./OWNED
Displays information for all spinlocks owned by a CPU. If no processors own any spinlocks, SDA displays the following message:
%SDA-I-NOSPLOWNED, all requested spinlocks are unowned/PCB
Displays all PCB-specific spinlocks./PORT
Displays all port spinlocks./PSHARED
Displays all process-shared (Pthreads) spinlocks./STATIC
Displays information for all static spinlocks in the system.
The SHOW SPINLOCKS command displays status and diagnostic information about the multiprocessing synchronization structures known as spinlocks.A static spinlock is a spinlock whose data structure is permanently assembled into the system. Static spinlocks are accessed as indexes into a vector of longword addresses called the spinlock vector, the address of which is contained in SMP$AR_SPNLKVEC. Table 4-29 lists the static spinlocks.
A dynamic spinlock is a spinlock that is created based on the configuration of a particular system. One such dynamic spinlock is the device lock SYSMAN creates when configuring a particular device. This device lock synchronizes access to the device's registers and certain UCB fields. The system creates a dynamic spinlock by allocating space from nonpaged pool, rather than assembling the lock into the system as it does in creating a static spinlock. Other types of dynamic spinlocks are: port spinlocks, mailbox spinlocks, PCB, cached PCB, process-shared, and miscellaneous spinlocks.
See the Writing OpenVMS Alpha Device Drivers in C for a full discussion of the role of spinlocks in maintaining synchronization of kernel-mode activities in a multiprocessing environment.
Table 4-29 Static Spinlocks Name Description QUEUEAST Spinlock for queuing ASTs at IPL 6 FILSYS Spinlock on file system structures LCKMGR Spinlock on all lock manager structures IOLOCK8/SCS Spinlock for executing a driver fork process at IPL 8 TX_SYNCH Transaction processing spinlock TIMER Spinlock for adding and deleting timer queue entries and searching the timer queue PORT Template structure for dynamic spinlocks for ports with multiple devices IO_MISC Miscellaneous short-term I/O spinlocks MMG Spinlock on memory management, PFN database, swapper, modified page writer, and creation of per-CPU database structures SCHED Spinlock on some process data structures and the scheduler database. IOLOCK9 Spinlock for executing a driver fork process at IPL 9 IOLOCK10 Spinlock for executing a driver fork process at IPL 10 IOLOCK11 Spinlock for executing a driver fork process at IPL 11 MAILBOX Spinlock for sending messages to the permanent system (OPCOM, JOBCTL, and so on) mailboxes POOL Spinlock on nonpaged pool database PERFMON Spinlock for I/O performance monitoring INVALIDATE Spinlock for system space translation buffer (TB) invalidation HWCLK Spinlock on hardware clock database, including the quadword containing the due time of the first timer queue entry (EXE$GQ_1ST_TIME) and the quadword containing the system time (EXE$GQ_SYSTIME) MEGA Spinlock for serializing access to fork-wait queue EMB/MCHECK Spinlock for allocating and releasing error-logging buffers and synchronizing certain machine error handling For each spinlock in the system, SHOW SPINLOCKS provides the following information:
- Name of the spinlock (or device name for the device lock)
- Address of the spinlock data structure (SPL)
- The owning CPU's CPU ID
- IPL at which allocation of the lock is synchronized on a local processor
- Number of nested acquisitions of the spinlock by the processor owning the spinlock (Ownership Depth)
- Rank of the spinlock
- Timeout interval for spinlock acquisition (in terms of 10 milliseconds)
- Shared array (shared spinlock context block pointer)
- Number of processors waiting to obtain the spinlock
- Interlock (synchronization mutex used when full-checking multiprocessing is enabled)
The last two items (CPUs waiting and Interlock) are only displayed if full-checking multiprocessing is enabled.
SHOW SPINLOCKS/BRIEF produces a condensed display of this same information, excluding the share array and timeout interval.
SHOW SPINLOCKS/COUNTS displays only the Spin, Wait, and Acquire counts for each spinlock.
If the system under analysis was executing with full-checking multiprocessing enabled, SHOW SPINLOCKS/FULL adds to the spinlock display the Spin, Wait, and Acquire counts and the last sixteen PCs at which the lock was acquired or released. If applicable, SDA also displays the PC of the last release of multiple, nested acquisitions of the lock.
If no spinlock name, address, or index is given, then information is displayed for all applicable spinlocks.
| #1 |
|---|
SDA> SHOW SPINLOCKS
System static spinlock structures
---------------------------------
EMB Address 810AE300
Owner CPU ID None IPL 0000001F
Ownership Depth FFFFFFFF Rank 00000000
Timeout Interval 000186A0 Share Array 00000000
CPUs Waiting 00000000 Interlock Free
MCHECK Address 810AE300
Owner CPU ID None IPL 0000001F
Ownership Depth FFFFFFFF Rank 00000000
Timeout Interval 000186A0 Share Array 00000000
CPUs Waiting 00000000 Interlock Free
MEGA Address 810AE400
Owner CPU ID None IPL 0000001F
Ownership Depth FFFFFFFF Rank 00000002
Timeout Interval 000186A0 Share Array 00000000
CPUs Waiting 00000000 Interlock Free
HWCLK Address 810AE500
Owner CPU ID None IPL 00000016
Ownership Depth FFFFFFFF Rank 00000004
Timeout Interval 000186A0 Share Array 00000000
CPUs Waiting 00000000 Interlock Free
.
.
.
System dynamic spinlock structures
----------------------------------
QTV14$OPA Address 8103FB00
Owner CPU ID None DIPL 00000015
Ownership Depth FFFFFFFF Rank FFFFFFFF
Timeout Interval 000186A0 Share Array 00000000
CPUs Waiting 00000000 Interlock Free
QTV14$MBA Address 810AE900
Owner CPU ID None IPL 0000000B
Ownership Depth FFFFFFFF Rank 0000000C
Timeout Interval 000186A0 Share Array 00000000
CPUs Waiting 00000000 Interlock Free
QTV14$NLA Address 810AE900
Owner CPU ID None IPL 0000000B
Ownership Depth FFFFFFFF Rank 0000000C
Timeout Interval 000186A0 Share Array 00000000
CPUs Waiting 00000000 Interlock Free
QTV14$PKA Address 814AA100
Owner CPU ID None DIPL 00000015
Ownership Depth FFFFFFFF Rank FFFFFFFF
Timeout Interval 000186A0 Share Array 00000000
CPUs Waiting 00000000 Interlock Free
.
.
.
|
This excerpt illustrates the default output of the SHOW SPINLOCKS command.
| #2 |
|---|
SDA> SHOW SPINLOCKS/BRIEF
System static spinlock structures
---------------------------------
Spinlock Owner CPUs
Address Name IPL Rank Depth CPU Waiting Interlock
-------- ------------ ---- -------- -------- -------- -------- ---------
810AE300 EMB 001F 00000000 FFFFFFFF None 00000000 Free
810AE300 MCHECK 001F 00000000 FFFFFFFF None 00000000 Free
810AE400 MEGA 001F 00000002 FFFFFFFF None 00000000 Free
810AE500 HWCLK 0016 00000004 FFFFFFFF None 00000000 Free
810AE600 INVALIDATE 0015 00000006 FFFFFFFF None 00000000 Free
810AE700 PERFMON 000F 00000008 FFFFFFFF None 00000000 Free
810AE800 POOL 000B 0000000A FFFFFFFF None 00000000 Free
810AE900 MAILBOX 000B 0000000C FFFFFFFF None 00000000 Free
810AEA00 IOLOCK11 000B 0000000E FFFFFFFF None 00000000 Free
810AEB00 IOLOCK10 000A 0000000F FFFFFFFF None 00000000 Free
810AEC00 IOLOCK9 0009 00000010 FFFFFFFF None 00000000 Free
810AED00 SCHED 0008 00000012 00000000 00000000 00000001 Free
810AEE00 MMG 0008 00000014 FFFFFFFF None 00000000 Free
810AEF00 IO_MISC 0008 00000016 FFFFFFFF None 00000000 Free
810AF000 PORT 0008 00000017 FFFFFFFF None 00000000 Free
810AF100 TIMER 0008 00000018 00000000 00000000 00000000 Free
810AF200 TX_SYNCH 0008 00000019 FFFFFFFF None 00000000 Free
810AF300 SCS 0008 0000001A FFFFFFFF None 00000000 Free
810AF400 LCKMGR 0008 0000001B FFFFFFFF None 00000000 Free
810AF500 FILSYS 0008 0000001C FFFFFFFF None 00000000 Free
810AF600 QUEUEAST 0006 0000001E FFFFFFFF None 00000000 Free
System dynamic spinlock structures
----------------------------------
Device Owner CPUs
Address Name DIPL Rank Depth CPU Waiting Interlock
-------- ------------ ---- -------- -------- -------- -------- ---------
8103FB00 QTV14$OPA 0015 FFFFFFFF FFFFFFFF None 00000000 Free
810AE900 QTV14$MBA 000B 0000000C FFFFFFFF None 00000000 Free
810AE900 QTV14$NLA 000B 0000000C FFFFFFFF None 00000000 Free
814AA100 QTV14$PKA 0015 FFFFFFFF FFFFFFFF None 00000000 Free
.
.
.
|
This excerpt illustrates the condensed form of the display produced in the first example.
| #3 |
|---|
SDA> SHOW SPINLOCKS/FULL SCHED
System static spinlock structures
---------------------------------
SCHED Address 810AED00
Owner CPU ID 00000000 IPL 00000008
Ownership Depth 00000000 Rank 00000012
Timeout Interval 002DC6C0 Share Array 00000000
CPUs Waiting 00000001 Interlock Free
Spins 00000000.0458E8DC Busy waits 00252E8D
Acquires 00000000.01279BE0
Spinlock SPL$C_SCHED was last acquired or released from:
(Most recently) 8004AD00 EXE$SWTIMER_FORK_C+00170
. 8004B1D4 EXE$SWTIMER_FORK_C+00644
. 8004AD00 EXE$SWTIMER_FORK_C+00170
. 8004B1D4 EXE$SWTIMER_FORK_C+00644
. 8004AD00 EXE$SWTIMER_FORK_C+00170
. 8004B1D4 EXE$SWTIMER_FORK_C+00644
. 8004AD00 EXE$SWTIMER_FORK_C+00170
. 8004B1D4 EXE$SWTIMER_FORK_C+00644
. 8004AD00 EXE$SWTIMER_FORK_C+00170
. 80136A2C SCH$INTERRUPT+0070C
. 80117580 SCH$IDLE_C+002A0
. 8004B230 EXE$SWTIMER_FORK_C+006A0
. 8004AFC4 EXE$SWTIMER_FORK_C+00434
. 80117360 SCH$IDLE_C+00080
. 8012E5F4 EXE$HIBER_INT_C+00074
(Least recently) 80132150 EXE$SCHDWK_C+00110
Last release of multiple acquisitions occurred at:
80262A54 EXE$CHECK_VERSION_C+009F4
|
This display shows the detailed information on the SCHED spinlock, including the PC history.
Displays the location and contents of the process stacks (of the SDA current process) and the system stack.
SHOW STACK {range | /ALL | [/EXECUTIVE | /INTERRUPT | /KERNEL | /PHYSICAL | /SUMMARY | /SUPERVISOR | /SYSTEM | /USER]}
{/LONG | /QUAD (d)}
range
Range of memory locations you want to display in stack format. You can express a range using the following syntax:
m:n Range of addresses from m to n m;n Range of addresses starting at m and continuing for n bytes
/ALL
Displays the locations and contents of the four process stacks for the SDA current process and the system stack./EXECUTIVE
Shows the executive stack for the SDA current process./INTERRUPT
Shows the system stack and is retained for compatibility with OpenVMS VAX. The interrupt stack does not exist on OpenVMS Alpha and OpenVMS Integrity servers./KERNEL
Shows the kernel stack for the SDA current process./LONG
Displays longword width stacks. If you do not specify this qualifier, SDA by default displays quadword width stacks./PHYSICAL
Treats the start and end addresses in the given range as physical addresses. This qualifier is only relevant when a range is specified. By default, SDA treats range addresses as virtual addresses./QUAD
Displays quadword width stacks. This is the default./SUMMARY
Displays a list of all known stack ranges and the current stack pointer for each range./SUPERVISOR
Shows the supervisor stack for the SDA current process./SYSTEM
Shows the system stack./USER
Shows the user stack for the SDA current process.
The SHOW STACK command, by default, displays the stack that was in use when the system failed, or, in the analysis of a running system, the current operating stack. For a process that became the SDA current process as the result of a SET PROCESS command, the SHOW STACK command by default shows its current operating stack.The various qualifiers to the command allow display of any of the four per-process stacks for the SDA current process, as well as the system stack for the SDA current CPU. In addition, any given range can be displayed in stack format.
You can define SDA process and CPU context by using the SET CPU, SHOW CPU, SHOW CRASH, SET PROCESS, and SHOW PROCESS commands as indicated in their command descriptions. A complete discussion of SDA context control appears in Section 2.5.
SDA provides the following information in each stack display:
Section Contents Identity of stack SDA indicates whether the stack is a process stack (user, supervisor, executive, or kernel) or the system stack. Stack pointer The stack pointer identifies the top of the stack. The display indicates the stack pointer by the symbol SP =>. Stack address SDA lists all the addresses that the operating system has allocated to the stack. The stack addresses are listed in a column that increases in increments of 8 bytes (one quadword) unless you specify the /LONG qualifier, in which case addresses are listed in increments of 4 (one longword). Stack contents SDA lists the contents of the stack in a column to the right of the stack addresses. Symbols SDA attempts to display the contents of a location symbolically, using a symbol and an offset. If the stack is being displayed in quadword width and the location cannot be symbolized as a quadword, SDA attempts to symbolize the least significant longword and then the most significant longword. If the address cannot be symbolized, this column is left blank.
Canonical stack When displaying the kernel stack of a noncurrent process in a crash dump, SDA identifies the stack locations used by the scheduler to store the register contents of the process. Mechanism array
Signal array
Exception frameWhen displaying the current stack in a FATALEXCPT, INVEXCEPTN, SSRVEXCEPT, or UNXSIGNAL bugcheck, SDA identifies the stack locations used to store registers and other key data for these structures. If a stack is empty, the display shows the following:
SP => (STACK IS EMPTY)
#1
SDA> SHOW STACK Current Operating Stack (SYSTEM): FFFFFFFF.8244BD08 FFFFFFFF.800600FC SCH$REPORT_EVENT_C+000FC FFFFFFFF.8244BD10 00000000.00000002 FFFFFFFF.8244BD18 00000000.00000005 FFFFFFFF.8244BD20 FFFFFFFF.8060C7C0 SP => FFFFFFFF.8244BD28 FFFFFFFF.8244BEE8 FFFFFFFF.8244BD30 FFFFFFFF.80018960 EXE$HWCLKINT_C+00260 FFFFFFFF.8244BD38 00000000.000001B8 FFFFFFFF.8244BD40 00000000.00000050 FFFFFFFF.8244BD48 00000000.00000210 UCB$N_RSID+00002 FFFFFFFF.8244BD50 00000000.00000000 FFFFFFFF.8244BD58 00000000.00000000 FFFFFFFF.8244BD60 FFFFFFFF.804045D0 SCH$GQ_IDLE_CPUS FFFFFFFF.8244BD68 FFFFFFFF.8041A340 EXE$GL_FKWAITFL+00020 FFFFFFFF.8244BD70 00000000.00000250 UCB$T_MSGDATA+00034 FFFFFFFF.8244BD78 00000000.00000001 CHF$IS_MCH_ARGS FFFFFFFF.8244BD80 00000000.0000002B CHF$PH_MCH_FRAME FFFFFFFF.8244BD88 FFFFFFFF.8244BFB0 CHF$IS_MCH_DEPTH FFFFFFFF.8244BD90 80000000.FFFFFFFD G CHF$PH_MCH_DADDR FFFFFFFF.8244BD98 00000000.00001600 CTL$C_CLIDATASZ+00060 CHF$PH_MCH_ESF_ADDR FFFFFFFF.8244BDA0 FFFFFFFF.8244BF40 CHF$PH_MCH_SIG_ADDR FFFFFFFF.8244BDA8 FFFFFFFF.8244BEE8 CHF$IH_MCH_SAVR0 FFFFFFFF.8244BDB0 FFFFFFFF.8041FB00 SMP$RELEASEL+00640 CHF$IH_MCH_SAVR1 FFFFFFFF.8244BDB8 00000000.00000000 CHF$IH_MCH_SAVR16 FFFFFFFF.8244BDC0 00000000.0000000D CHF$IH_MCH_SAVR17 FFFFFFFF.8244BDC8 0000FFF0.00007E04 CHF$IH_MCH_SAVR18 FFFFFFFF.8244BDD0 00000000.00000000 CHF$IH_MCH_SAVR19 FFFFFFFF.8244BDD8 00000000.00000001 CHF$IH_MCH_SAVR20 FFFFFFFF.8244BDE0 00000000.00000000 CHF$IH_MCH_SAVR21 FFFFFFFF.8244BDE8 FFFFFFFF.805AE4B6 SISR+0006E CHF$IH_MCH_SAVR22 FFFFFFFF.8244BDF0 00000000.00000001 CHF$IH_MCH_SAVR23 FFFFFFFF.8244BDF8 00000000.00000010 CHF$IH_MCH_SAVR24 FFFFFFFF.8244BE00 00000000.00000008 CHF$IH_MCH_SAVR25 FFFFFFFF.8244BE08 00000000.00000010 CHF$IH_MCH_SAVR26 FFFFFFFF.8244BE10 00000000.00000001 CHF$IH_MCH_SAVR27 FFFFFFFF.8244BE18 00000000.00000000 CHF$IH_MCH_SAVR28 FFFFFFFF.8244BE20 FFFFFFFF.804045D0 SCH$GQ_IDLE_CPUS FFFFFFFF.8244BE28 30000000.00000300 UCB$L_PI_SVA FFFFFFFF.8244BE30 FFFFFFFF.80040F6C EXE$REFLECT_C+00950 FFFFFFFF.8244BE38 18000000.00000300 UCB$L_PI_SVA FFFFFFFF.8244BE40 FFFFFFFF.804267A0 EXE$CONTSIGNAL+00228 FFFFFFFF.8244BE48 00000000.7FFD00A8 PIO$GW_IIOIMPA FFFFFFFF.8244BE50 00000003.00000000 FFFFFFFF.8244BE58 FFFFFFFF.8003FC20 EXE$CONNECT_SERVICES_C+00920 FFFFFFFF.8244BE60 FFFFFFFF.8041FB00 SMP$RELEASEL+00640 FFFFFFFF.8244BE68 00000000.00000000 FFFFFFFF.8244BE70 FFFFFFFF.8042CD50 SCH$WAIT_PROC+00060 FFFFFFFF.8244BE78 00000000.0000000D FFFFFFFF.8244BE80 0000FFF0.00007E04 FFFFFFFF.8244BE88 00000000.00000000 FFFFFFFF.8244BE90 00000000.00000001 FFFFFFFF.8244BE98 00000000.00000000 FFFFFFFF.8244BEA0 FFFFFFFF.805AE4B6 SISR+0006E FFFFFFFF.8244BEA8 00000000.00000001 FFFFFFFF.8244BEB0 00000000.00000010 FFFFFFFF.8244BEB8 00000000.00000008 FFFFFFFF.8244BEC0 00000000.00000010 FFFFFFFF.8244BEC8 00000000.00000001 FFFFFFFF.8244BED0 00000000.00000000 FFFFFFFF.8244BED8 FFFFFFFF.804045D0 SCH$GQ_IDLE_CPUS FFFFFFFF.8244BEE0 00000000.00000001 CHF$L_SIG_ARGS FFFFFFFF.8244BEE8 0000000C.00000005 CHF$L_SIG_ARG1 FFFFFFFF.8244BEF0 FFFFFFFC.00010000 SYS$K_VERSION_08 FFFFFFFF.8244BEF8 00000300.FFFFFFFC UCB$L_PI_SVA FFFFFFFF.8244BF00 00000002.00000001 FFFFFFFF.8244BF08 00000000.0000000C FFFFFFFF.8244BF10 00000000.00000000 FFFFFFFF.8244BF18 00000000.FFFFFFFC FFFFFFFF.8244BF20 00000008.00000000 FFFFFFFF.8244BF28 00000000.00000001 FFFFFFFF.8244BF30 00000008.00000000 FFFFFFFF.8244BF38 00000000.FFFFFFFC INTSTK$Q_R2 FFFFFFFF.8244BF40 FFFFFFFF.80404668 SCH$GL_ACTIVE_PRIORITY INTSTK$Q_R3 FFFFFFFF.8244BF48 FFFFFFFF.8042F280 SCH$WAIT_KERNEL_MODE INTSTK$Q_R4 FFFFFFFF.8244BF50 FFFFFFFF.80615F00 INTSTK$Q_R5 FFFFFFFF.8244BF58 00000000.00000000 INTSTK$Q_R6 FFFFFFFF.8244BF60 FFFFFFFF.805AE000 INTSTK$Q_R7 FFFFFFFF.8244BF68 00000000.00000000 INTSTK$Q_PC FFFFFFFF.8244BF70 00000000.FFFFFFFC INTSTK$Q_PS FFFFFFFF.8244BF78 30000000.00000300 UCB$L_PI_SVA FFFFFFFF.8244BF80 FFFFFFFF.80404668 SCH$GL_ACTIVE_PRIORITY FFFFFFFF.8244BF88 00000000.7FFD00A8 PIO$GW_IIOIMPA FFFFFFFF.8244BF90 00000000.00000000 FFFFFFFF.8244BF98 FFFFFFFF.8042CD50 SCH$WAIT_PROC+00060 FFFFFFFF.8244BFA0 00000000.00000044 FFFFFFFF.8244BFA8 FFFFFFFF.80403C30 SMP$GL_FLAGS Prev SP (8244BFB0) => FFFFFFFF.8244BFB0 FFFFFFFF.8042CD50 SCH$WAIT_PROC+00060 FFFFFFFF.8244BFB8 00000000.00000000 FFFFFFFF.8244BFC0 FFFFFFFF.805EE040 FFFFFFFF.8244BFC8 FFFFFFFF.8006DB54 PROCESS_MANAGEMENT_NPRO+0DB54 FFFFFFFF.8244BFD0 FFFFFFFF.80404668 SCH$GL_ACTIVE_PRIORITY FFFFFFFF.8244BFD8 FFFFFFFF.80615F00 FFFFFFFF.8244BFE0 FFFFFFFF.8041B220 SCH$RESOURCE_WAIT FFFFFFFF.8244BFE8 00000000.00000044 FFFFFFFF.8244BFF0 FFFFFFFF.80403C30 SMP$GL_FLAGS FFFFFFFF.8244BFF8 00000000.7FF95E00
The SHOW STACK command displays a system stack on an OpenVMS Alpha system. The data shown before the stack pointer may not be valid. The mechanism array, signal array, and exception frame symbols displayed on the left appear only for INVEXCEPTN, FATALEXCPT, UNXSIGNAL, and SSRVEXCEPT bugchecks.
#2
SDA> SHOW STACK/SUMMARY Stack Ranges ------------ Memory Stack: Stack Stack Base Stack Limit Stack Pointer Notes ----------- ----------------- ----------------- ----------------- --------- Kernel 00000000.7FF44000 00000000.7FF2C000 00000000.7FF43EB0 Current Executive 00000000.7FF68000 00000000.7FF58000 00000000.7FF68000 Supervisor 00000000.7FFAC000 00000000.7FFA8000 00000000.7FFAC000 User 00000000.3FFE2000 00000000.3FFCA000 00000000.3FFE1FB0 KPstack User 00000000.3FFFE000 00000000.3FFE6000 00000000.3FFFDDB0 KPstack User 00000000.7AC9E000 00000000.7AC9A000 00000000.7AC9D830 System FFFFFFFF.86970000 FFFFFFFF.86958000 FFFFFFFF.8696FFC0 Register Stack: Stack Stack Base Stack Limit Stack Pointer Notes ----------- ----------------- ----------------- ----------------- --------- Kernel 00000000.7FF12000 00000000.7FF2A000 00000000.7FF12250 Current Executive 00000000.7FF46000 00000000.7FF56000 00000000.7FF46000 Supervisor 00000000.7FF6A000 00000000.7FF8A000 00000000.7FF6A000 User 000007FD.BFF3C000 000007FD.BFF54000 000007FD.BFF3C160 KPstack User 000007FD.BFF58000 000007FD.BFF70000 000007FD.BFF58108 KPstack User 000007FD.C0000000 000007FD.C0002000 000007FD.C0000268 System FFFFF802.0F236000 FFFFF802.0F24E000 FFFFF802.0F236278
This example shows the stack ranges for a process on an OpenVMS Integrity server system.
| Previous | Next | Contents | Index |