Maybe one of the experts can give me a hint.
I get permanent errors reported in binary.errorlog
uerf -R reports "CPU EXCEPTION" every second.
I tried to get more info with dia, and I am clueless with the
details.
Here is the dia output (shortened, very long...):
TIA
Heiko Weier
DECevent V2.6
******************************** ENTRY 1
********************************
Logging OS 2. Digital UNIX
System Architecture 2. Alpha
Event sequence number 31907.
Timestamp of occurrence 17-NOV-2000 14:57:18
Host name hhdbs1
System type register x00000009 AlphaServer 2x00
Number of CPUs (mpnum) x00000001
CPU logging event (mperr) x00000000
Event validity 1. O/S claims event is valid
Event severity 1. Severe Priority
Entry type 100. CPU Machine Check Errors
CPU Minor class 2. 660 Entry
-- ENTRY FRAME FOLLOWS --
Frame ID x00000002 Machine Check Frame
Byte Count x00000220
Byte Count x0220
Processor Specific Offset x00000110
System Specific Offset x000001A0
PAL Error Type Code x0000008A Bugchk Generated by OS specific
PALcode
PAL Frame Revision x00000001
- ALPHA CHIP REGISTERS -
PALTEMP1 x0000000000000001
PALTEMP2 x001102F800000004
PALTEMP3 xFFFFFC00152F7EC0
PALTEMP4 x000003FFC00871D0
PALTEMP5 x000000000000006D
PALTEMP6 x0000000000000240
PALTEMP7 x0000000000004200
PALTEMP8 x0000000000000400
PALTEMP9 x0000000000000000
PALTEMP10 xFFFFFC00003F7A80
PALTEMP11 x0000000000000000
PALTEMP12 xFFFFFC00003F7E40
PALTEMP13 xFFFFFC00003F7E70
PALTEMP14 xFFFFFC00003F7ED0
PALTEMP15 xFFFFFC00003F7C10
PALTEMP16 xFFFFFC00003F7790
PALTEMP17 x0000000000019410
PALTEMP18 x000000011FFFF2D0
PALTEMP19 xFFFFFFFFA1F03A38
PALTEMP20 xFFFFFC000056D6F0
PALTEMP21 x0000000000000000
PALTEMP22 x40424272727E7E7E
PALTEMP23 x0000000000000000
PALTEMP24 x0000000000000000
PALTEMP25 x0000000000010000
PALTEMP26 x0000000040067408
PALTEMP27 x0000000000000000
PALTEMP28 x0000000016B68000
PALTEMP29 xFFFFFFFC00000000
PALTEMP30 x0000000000000001
PALTEMP31 x00000000062ADA38
Exception Address Reg xFFFFFC000041EB2C
Exception Address Reg Provides
Information
About The Most Recent Exception.
Address Points to Native-Mode
Instruction
If Machine Check or Math Trap
Exception,
On Return Subtract 4 from
Exception PC.
Last Exception Addr PC:
x3FFFFF0000107ACB
Exception Summary Reg x0000000000000000
Exception Mask Reg x0000000000000000
Icache Ctrl & Status Reg x001102F800000004
Performance Counters Disabled
Empty Wrt Buffer Before Issuing
Next Inst
Branch Prediction Selection: Not
Taken
JSR Stack is Disabled
Instructions Can Only Single Issue
If Not in PALmode, Executing
Reserved Inst
Opcode Will Result in OPCDEC
Exception.
Super Page Istream Memory Mapping
Disabled
Float Point Inst Will Cause FEN
Exception
Icache Addr Space Numb:
x0000000000000000
PALcode Base Address Reg x0000000000014000
PALcode Base Address:
x0000000000000005
Hardware Int Enable Reg x0000000000001CF0
CRD Error Interrupts Enabled
CPU Hrdw Interrupts Enbld Irq_h
Pins 0,1,2
CPU Hrdw Interrupts Enbld Irq_h
Pins 3,4,5
Performance Cntr 0 & 1 Interrupts
Disabled
Serial Line Interrupts Disabled
NO AST Interrupts Enabled In Any
Mode
Hardware Int Request Reg x0000000000000000
NO Hrdw Int Req With Companion
Enable Set
NO Softw Int Req With Companion
Enable Set
NO AST Int Req With Companion
Enable Set
Memory Management CSR x0000000000005ADB
MMCSR Valid Only on Mem Mgt Err,
DTB Miss,
D-Stream Fault, Dcache Parity
Error.
D-Stream Reference Error Caused by
Write
D-Stream Reference Caused Access
Violation
Write D-Stream Ref w/ PTE
Fault-on-Wrt Set
Last Faulting Instruction RA Field:
R13
Last Faulting Instruction Opcode
Follows:
x2D - STQ Store Quadword
(Data) Cache Status Reg x0000000000000003
This is EV45 Cache Status
Register(C_STAT)
EV45 Chip is Production Version of
21064A
Last Load or Store Missed Dcache
Cache Address Reg x00000007FFFFFFFF
Abox Control Reg x000000000000142E
Machine Checks Enabled for Uncorr
Errors
CRD Interrupts Enabled
Single Entry Icache Stream Buffer
Enabled
Enable Super Page Dstream Virtual
Addr Map
VA<33:13> to PA<33:13>, if
VA<42:41>=2.
Lock Operation Conforms to Alpha
Architect
Dcache Enabled
16K Byte Dcache Selected
Bus Interface Status Reg x0000000000000240
Bus Interface Address Reg x0000000000019410
Address Only Valid if Bus Interface
Status
Register Error Bit 0,1,2, or 3
is Set.
BIU Addr adr_h <4:2>: x4
BIU Addr adr_h<33:5>:
x0000000000000CA0
Bus Interface Control Reg x0000000E3000E557
External Cache (Bcache) Enabled
ECC MODE: External Cache ECC
Enabled
Cache Rams are Output Enable
Controlled
Ext Cache Rd Access Time: 6 CPU
Cycles
Ext Cache Wrt Cycle Time: 6 CPU
Cycles
Received on Fri Nov 17 2000 - 15:07:01 NZDT