Maybe some of the experts can give me a hint on permanent reported "CPU
EXCEPTIONS" (uerf says so).
I have upgraded the memory 2 months ago, with no failure mentioned.
Since 2 weeks the failure is permanent ...
TIA
Heiko Weier
Here is a dia -o brief output:
DECevent V2.6
******************************** ENTRY 1
********************************
Logging OS 2. Digital UNIX
System Architecture 2. Alpha
Event sequence number 31907.
Timestamp of occurrence 17-NOV-2000 14:57:18
Host name hhdbs1
System type register x00000009 AlphaServer 2x00
Number of CPUs (mpnum) x00000001
CPU logging event (mperr) x00000000
Event validity 1. O/S claims event is valid
Event severity 1. Severe Priority
CPU Minor class 2. 660 Entry
-- ENTRY FRAME FOLLOWS --
Frame ID x00000002 Machine Check Frame
- ALPHA CHIP REGISTERS -
Hardware Int Request Reg x0000000000000000
NO Hrdw Int Req With Companion Enable
Set
NO Softw Int Req With Companion
Enable Set
NO AST Int Req With Companion Enable
Set
Memory Management CSR x0000000000005ADB
MMCSR Valid Only on Mem Mgt Err, DTB
Miss,
D-Stream Fault, Dcache Parity
Error.
D-Stream Reference Error Caused by
Write
D-Stream Reference Caused Access
Violation
Write D-Stream Ref w/ PTE
Fault-on-Wrt Set
Last Faulting Instruction RA Field:
R13
Last Faulting Instruction Opcode
Follows:
x2D - STQ Store Quadword
(Data) Cache Status Reg x0000000000000003
This is EV45 Cache Status
Register(C_STAT)
EV45 Chip is Production Version of
21064A
Last Load or Store Missed Dcache
Bus Interface Status Reg x0000000000000240
Bcache Tag Reg x449018850A6C4848
Last Bcache Access Resulted in a Miss
Parity Bit for Bcache Tag Status Bits
Clr
Bcache Tag Dirty Bit Clear
Bcache Tag Shared Bit Set
Bcache Tag Valid Bit Clear
Bcache Tag Addrress Parity Bit
Asserted
Tag Being Probed: x0000000000016242
- SYSTEM SPECIFIC REGS -
Bcache Corr Error (R1) x0000000000000000
Bits in LOW LONGWORD SLICE
Follows
LW0 EDC Syndrome: x0000000000000000
LW2 EDC Syndrome: x0000000000000000
Bits in HIGH LONGWORD SLICE
Follows
LW1 EDC Syndrome: x0000000000000000
LW3 EDC Syndrome: x0000000000000000
Bcache Uncorr Err Adr(R4) x00300CBD00300CBD
Bits in LOW LONGWORD SLICE
Follows
Sys-Bus Last Predicted Tag Parity
Bit: Clr
Tag Parity Bit CLR - Last Bc Loc
Accessed
Last LW0/LW2 MAP Index:
x0000000000000CBD
Last LW0/LW2 Tag Field:
x0000000000000006
Bits in HIGH LONGWORD SLICE
Follows
Sys-Bus Last Predicted Tag Parity
Bit: Clr
Tag Parity Bit CLR - Last Bc Loc
Accessed
Last LW1/LW3 MAP Index:
x0000000000000CBD
Last LW1/LW3 Tag Field:
x0000000000000006
Duplicate Tag Err Reg(R5) x37B5EAF837B5EAF8
Bits in LOW LONGWORD SLICE
Follows
Last Dup Tag Stor Offst
x00000000000000BE
Dup Tag BANK-0 Parity CLR -Last Loc
Access
Dup Tag Stor BANK-0 Tag
x000000000000017A
Dup Tag BANK-1 Parity SET -Last Loc
Access
Dup Tag Stor BANK-1 Tag
x000000000000017B
Bits in HIGH LONGWORD SLICE
Follows
Last Dup Tag Stor Offst
x00000000000000BE
Dup Tag BANK-0 Parity CLR -Last Loc
Access
Dup Tag Stor BANK-0 Tag
x000000000000017A
Dup Tag BANK-1 Parity SET -Last Loc
Access
Dup Tag Stor BANK-1 Tag
x000000000000017B
System Bus Error Reg (R7) xCA003400C6000000
Bits in LOW LONGWORD SLICE
Follows
MADR <31:0> (R14) Has Valid Miss
Contents
6-Bit Bcache Miss Cntr:
x0000000000000023
Bits in HIGH LONGWORD SLICE
Follows
MADR <63:32> (R14) Has Valid Miss
Contents
6-Bit Bcache Miss Cntr:
x0000000000000025
-- ENTRY FRAME FOLLOWS --
Frame ID x00000011 T2 System-Bus to PCI Bridge Frame
IO Control/Status Reg xFE000084270C81B0
Bit 4 Set: PCI Slot 0 Present
Bit 5 Set: PCI Slot 0 Present
Bit 7 Set: TLB Error Checking Enabled
Bit 8 Set: CBUS CXACK Check Enabled
Bit 15 Set: PCI Slot 2 Present
Bit 18 Set: PCI Slot 1 Present
Bit 19 Set: PCI Slot 1 Present
Bit 24 Set: NOACK, CUCERR, OutOfSync
Enbld
Bit 25 Set: PCI Memory Space Enabled
Bit 26 Set: Translation Look-Aside
Enabled
Bit 29 Set: CBUS Parity Checking
Enabled
T2 Revision: Pass 3
State Machine Vis Select: CBUS Cyc
Counter
Bit 39 Set: PCI Slot 2 Present
Bit 57 Set: PCI NMI Interrupts
Enabled
Bit 58 Set: PCI Dev Timeout Inter
Enabled
Bit 59 Set: PCI SERR# Interrupts
Enabled
Bit 60 Set: PCI PERR# Interrupts
Enabled
Bit 61 Set: PCI Rd Data Prty Inter
Enabled
Bit 62 Set: PCI Adr Parity Inter
Enabled
Bit 63 Set: PCI Wrt Data Prty Inter
Enbled
CERR1 CBUS Error Reg 1 x0000000000000000
PERR1 PCI Error Reg 1 x0000000000000000
-- ENTRY FRAME FOLLOWS --
Frame ID x00000008 Memory Frame
Memory Module ID x00000000
Error Register 1 x000C000100000000
[Odd] Error Summary
[Odd] EDC Corr Error
[Odd] Missed EDC Corr Error
-- ENTRY FRAME FOLLOWS --
Frame ID x00000008 Memory Frame
Memory Module ID x00000001
NULL Memory Frame. The registers in
this
frame contain zeros
-- ENTRY FRAME FOLLOWS --
Frame ID x00000008 Memory Frame
Memory Module ID x00000002
NULL Memory Frame. The registers in
this
frame contain zeros
-- ENTRY FRAME FOLLOWS --
Frame ID x00000008 Memory Frame
Memory Module ID x00000003
NULL Memory Frame. The registers in
this
frame contain zeros
-- ENTRY FRAME FOLLOWS --
Frame ID x00000000 End Frame
Heiko Weier Universitaet Hamburg
Regionales Rechenzentrum
Tel. 040/42838-3081 Schlueterstrasse 70
0172-4527064
FAX 040/42838-3284 D-20146 Hamburg
PGP-KEY:
http://www.rrz.uni-hamburg.de/RRZ/rrz_info/Mitarbeiter/weier.pgp.txt
Received on Fri Nov 17 2000 - 15:18:55 NZDT